IDT72V51333L7-5BB8 IDT, Integrated Device Technology Inc, IDT72V51333L7-5BB8 Datasheet - Page 38

• Manufacturer Part Number: IDT72V51333L7-5BB8
• Description: IC FLOW CTRL MULTI QUEUE 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72V51333L7-5BB8

• Configuration: Dual
• Density: 512Kb
• Access Time (max): 4ns
• Word Size: 18b
• Organization: 4Kx18x8
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: BGA
• Clock Freq (max): 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Supply Current: 100mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V51333L7-5BB8

NOTE:
1. The waveform here shows the PAE flag operation when no queue switches are occurring and a queue selected on both the write and read ports is being written to then read
Cycle:
*A* Queue 3 of Device 1 is selected on the read port. A queue within Device 2 had previously been selected. The PAE flag output and the data outputs of device 1 are High-Impedance.
*B* No read occurs.
*C* The PAE flag output now switches to device 1. Word, Wn is read from Q3 due to the FWFT operation. This read operation from Q3 is at the almost empty boundary, therefore
*D* Q1 of device 1 is selected.
*E* The PAE flag goes LOW due to the read from Q3 2 RCLK cycles earlier. Word Wn+1 is read out due to the FWFT operation.
*F* Word, W0 is read from Q1 due to the FWFT operation. The PAE flag goes HIGH to show that Q1 is not almost empty.
IDT72V51333/72V51343/72V51353 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
WCLK
PAE
(Device 1)
PAE
(Device 2)
RCLK
RDADD
WEN
RADEN
REN
from at the almost empty boundary.
Flag Latencies:
Assertion: 2*RCLK + t
De-assertion: t
If t
PAE
RCLK
PAE will go LOW 2 RCLK cycles later.
SKEW2
REN
Qout
is violated there will be one extra RCLK cycle.
HIGH
HIGH-Z
HIGH-Z
SKEW2
t
t
CLKH
AS
t
QS
+ RCLK + t
RAE
D
t
ENS
*A*
1
n+1 words in Queue
t
Q
CLKL
3
t
QH
RAE
t
AH
t
ENH
t
SKEW2
*B*
Figure 20. Almost Empty Flag Timing and Queue Switch
t
RAE
t
OLZ
Figure 21. Almost Empty Flag Timing
*C*
t
A
t
AEHZ
t
AELZ
t
t
AS
QS
HIGH-Z
D
38
*D*
1
Q
D
1
t
ENS
1
t
QH
t
Q
AH
3
W
n
n+2 words in Queue
*E*
t
ENH
t
A
t
RAE
D
1
Q
3
1
W
*F*
n+1
COMMERCIAL AND INDUSTRIAL
t
A
t
RAE
TEMPERATURE RANGES
D
t
RAE
1
Q
1
*G*
W
2
0
t
n+1 words in Queue
A
D
1
Q
5940 drw22
1
5940 drw23
W
1