IDT72V51333L7-5BB8 IDT, Integrated Device Technology Inc, IDT72V51333L7-5BB8 Datasheet - Page 9

• Manufacturer Part Number: IDT72V51333L7-5BB8
• Description: IC FLOW CTRL MULTI QUEUE 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72V51333L7-5BB8

• Configuration: Dual
• Density: 512Kb
• Access Time (max): 4ns
• Word Size: 18b
• Organization: 4Kx18x8
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: BGA
• Clock Freq (max): 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Supply Current: 100mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V51333L7-5BB8

PIN DESCRIPTIONS (CONTINUED)
IDT72V51333/72V51343/72V51353 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
Symbol
RDADD
[6:0]
(Continued)
REN
SCLK
SENI
SENO
SI
SO
TCK
TDI
TDO
(2)
(2)
(2)
Read Address Bus
Read Enable
Serial Clock
Serial Input Enable
Serial Output Enable
Serial In
Serial Out
JTAG Clock
JTAG Test Data
Input
JTAG Test Data
Output
Name
I/O TYPE
OUTPUT has been completed. SENO follows SENI once programming of a device is complete. Therefore, SENO
OUTPUT to complete programming of all devices. The SI of a device connects to SO of the previous device in the
OUTPUT operation, test data serially loaded output via the TDO on the falling edge of TCK from either the Instruction
LVTTL
LVTTL
INPUT
LVTTL
INPUT
LVTTL
INPUT
INPUT
LVTTL
LVTTL
INPUT
LVTTL
INPUT
INPUT
LVTTL
LVTTL
LVTTL
queue to be read from can be selected via RCLK, RADEN and the RDADD address bus regardless
During serial programming of a multi-queue device, data loaded onto the SI input will be clocked into the
part (via a rising edge of SCLK), provided the SENI input of that device is LOW. If multiple devices are
Data present on SI will be loaded on a rising edge of SCLK provided that SENI is LOW. In expansion
data will be placed on to the Qout outputs from the newly selected queue, regardless of REN due to the
first word fall through effect.
The second function of the RDADD bus is to select the device of queues to be loaded on to the PAEn bus
during strobed flag mode. The most significant 3 bits, RDADD[6:4] are again used to select 1 of 8 possible
multi-queue devices that may be connected in expansion mode. Address bits RDADD[3:0] are don’t care
during device selection. The device address present on the RDADD bus will be selected on the rising
edge of RCLK provided that ESTR is HIGH, (note, that data can be placed on to the Qout bus, read from
the previously selected queue on this RCLK edge). Please refer to Table 2 for details on RDADD bus.
The REN input enables read operations from a selected queue based on a rising edge of RCLK. A
of the state of REN. Data from a newly selected queue will be available on the Qout output bus on the second
RCLK cycle after queue selection regardless of REN due to the FWFT operation. A read enable is not
required to cycle the PAEn bus (in polled mode) or to select the device , (in direct mode).
If serial programming of the multi-queue device has been selected during master reset, the SCLK input
clocks the serial data through the multi-queue device. Data setup on the SI input is loaded into the device
on the rising edge of SCLK provided that SENI is enabled, LOW. When expansion of devices is performed
the SCLK of all devices should be connected to the same source.
cascaded, the SENI input should be connected to the SENO output of the previous device. So when serial
loading of a given device is complete, its SENO output goes LOW, allowing the next device in the chain
to be programmed (SENO will follow SENI of a given device once that device is programmed). The SENI
input of the master device (or single device), should be controlled by the user.
This output is used to indicate that serial programming or default programming of the multi-queue device
will go LOW after programming provided SENI is LOW, once SENI is taken HIGH again, SENO will also
go HIGH. When the SENO output goes LOW, the device is ready to begin normal read/write operations.
If multiple devices are cascaded and serial programming of the devices will be used, the SENO output
should be connected to the SENI input of the next device in the chain. When serial programming of the
first device is complete, SENO will go LOW, thereby taking the SENI input of the next device LOW and
so on throughout the chain. When a given device in the chain is fully programmed the SENO output
essentially follows the SENI input. The user should monitor the SENO output of the final device in the chain.
When this output goes LOW, serial loading of all devices has been completed.
During serial programming this pin is loaded with the serial data that will configure the multi-queue devices.
mode the serial data input is loaded into the first device in a chain. When that device is loaded and its SENO
has gone LOW, the data present on SI will be directly output to the SO output. The SO pin of the first device
connects to the SI pin of the second and so on. The multi-queue device setup registers are shift registers.
This output is used in expansion mode and allows serial data to be passed through devices in the chain
chain. The SO of the final device in a chain should not be connected.
Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test
operations of the device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge
of TCK and outputs change on the falling edge of TCK. If the JTAG function is not used this signal needs
to be tied to GND.
One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan
operation,test data serially loaded via the TDI on the rising edge of TCK to either the Instruction Register,
ID Register and Bypass Register. An internal pull-up resistor forces TDI HIGH if left unconnected.
One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan
Register, ID Register and Bypass Register. This output is high impedance except when shifting, while in
SHIFT-DR and SHIFT-IR controller states.
9
Description
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES