IDT72P51777L7-5BBI IDT, Integrated Device Technology Inc, IDT72P51777L7-5BBI Datasheet

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FEATURES • • • • • Choose from among the following memory density options: ⎯ ⎯ ⎯ ⎯ ⎯ IDT72P51767 Total Available Memory = 5,242,880 bits ⎯ ⎯ ⎯ ⎯ ⎯ IDT72P51777 Total Available Memory = 10,485,760 bits • • ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits Features ......................................................................................................................................................................................................................... 1 Description ...................................................................................................................................................................................................................... 5 Pin configuration .............................................................................................................................................................................................................. 7 Detailed Description ......................................................................................................................................................................................................... 8 Pin Descriptions ............................................................................................................................................................................................................. 10 Pin number table ........................................................................................................................................................................................................... 15 Recommended DC ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits Figure 1. Multi-Queue Flow-Control Device Block Diagram ............................................................................................................................................. 6 Figure 2a. AC Test Load ................................................................................................................................................................................................ 18 Figure 2b. Lumped Capacitive Load, Typical Derating ................................................................................................................................................... 18 ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits List of Figures (Continued) Figure 55. Almost Empty Flag Timing ............................................................................................................................................................................. 76 Figure 56. PAEn - Direct Mode - Status Word Selection ................................................................................................................................................. 77 Figure ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits DESCRIPTION The IDT72P51767/ IDT72P51777 multi-queue flow-control devices are single chip solutions containing up to 128 configurable queues. All queues within the device have a common ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits WCLK WEN WCS 8 WRADD Write Control Logic WADEN Write Pointers PAF FSTR 8 General Flag PAFn Monitor FSYNC FXO FXI Active Q FF Flags ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits PIN CONFIGURATION A1 BALL PAD CORNER A GND GND D11 GND GND D12 D10 GND GND D13 D14 ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits DETAILED DESCRIPTION MULTI-QUEUE STRUCTURE The IDT multi-queue flow-control device has a single data input port and single data output port with up to 128 FIFO ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits Connecting three or more 10G Multi-Queue 128Q in Expansion mode using WRADD bit 7 / RDADD bit 7 for device connection details. 10Gbps MULTI-QUEUE DIFFERENCES ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits PIN DESCRIPTIONS Symbol & Name I/O TYPE (Pin No.) BM [3:0] Bus Matching 1.8V LVTTL (BM3-BB13 INPUT BM2-AA12 BM1-BB12 BM0-BB11) BOI Back Off One HSTL ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits PIN DESCRIPTIONS (CONTINUED) Symbol & Name I/O TYPE Pin No. FF (Continued) Full Flag HSTL (E1) OUTPUT FM Flag Mode 1.8V LVTTL (U2) INPUT PAFn ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits PIN DESCRIPTIONS (CONTINUED) Symbol & Name I/O TYPE Pin No. OE Output Enable HSTL (R22) INPUT PAE Programmable HSTL (N20) Almost-Empty OUTPUT Flag PAEn[7:0] Programmable ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits PIN DESCRIPTIONS (CONTINUED) Symbol & Name I/O TYPE Pin No. RCLK (Cont'd) Read Clock HSTL (J22) INPUT RCS Read Chip HSTL (J21) Select INPUT RDADD[7:0] ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits PIN DESCRIPTIONS (CONTINUED) Symbol & Name I/O TYPE (Pin No.) TDI JTAG Test Data HSTL (A11) INPUT TDO JTAG Test Data HSTL (B11) Output TP ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits PIN DESCRIPTIONS (CONTINUED) Symbol & Name I/O TYPE Pin No. VDD +1.8V Supply Power (See below) VDDQ Output Voltage Power (See below) Vref Reference INPUT ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits ABSOLUTE MAXIMUM RATINGS Symbol Rating V Terminal Voltage TERM with respect to GND T Storage Temperature STG I DC Output Current OUT NOTES: 1. Stresses ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits DC ELECTRICAL CHARACTERISTICS (Commercial 1.8V ± 0.10V 0°C to +70°C;Industrial Symbol Parameter I Input Leakage Current LI I ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits HSTL 1.5V AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels NOTE 1.5V ± 0.1V. ...

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... COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Com'l and Ind'l IDT72P51767L7-5 IDT72P51777L7-5 Min. Max. Unit — 133 MHz -1.2 1.2 ns 0.8 3.8 ns 7.5 — ns 3.0 — ns 3.0 — ...

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... Industrial temperature range product for the 7-5ns is available as a standard device. All other speed grades available by special order. 2. Values guaranteed by design, not currently tested. = 1.8V ± 0.10V -40°C to +85°C; JEDEC JESD8-A compliant Commercial IDT72P51767L6 IDT72P51767L7-5 IDT72P51777L6 IDT72P51777L7-5 Min. Max. 0.6 3.6 0.6 3.6 0.6 3.6 0.6 3 ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits XGMII REFERENCE SPECIFICATION The XGMII uses 1.5V High Speed Transceiver Logic (HSTL) signal levels. The electrical characteristics of the XGMII are specified such that the ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits FUNCTIONAL DESCRIPTION MASTER RESET A Master Reset is performed by toggling the MRS input from HIGH to LOW to HIGH. During a master reset all ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits TABLE 5 — SETTING THE QUEUE PROGRAMMING MODE DURING MASTER RESET Default Mode /MRS (DFM) ↑ 0 ↑ 0 ↑ 0 ↑ 0 ↑ 0 ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits SERIAL PROGRAMMING The multi-queue flow-control device is a fully programmable device, provid- ing the user with flexibility in how queues are configured in terms of ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits PAE: This is the 3 26-bit word and represents the Programmable Almost Empty (PAE) value. Each queue requires an individual PAE value. The PAE value ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits The following is an explanation of the binary file created by the C program for the 10G MQ devices (IDT72P51767/72P51777). The Desired Device Configuration is; ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits DEFAULT PROGRAMMING During a Master Reset if the DFM (Default Mode) input is HIGH the multi- queue device will be configured for default programming, (serial ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits TABLE 7 — PARALLEL PROGRAMMING MODE QUEUE CONFIGURATION EXAMPLE (1) WRADD/RDADD[7:0] 128 Queues/Device 64 Queues/Device 32 Queues/Device 16 Queues/Device 8 Queues/Device 4 Queues/Device 1 Queue/Device ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits When Multi-Queue devices are connected in an Expansion Configuration, the SENI signal of the first device in a chain must be held LOW. The SENO ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits PLL ON VS PLL OFF MODES The PLL has a frequency response rate of 85-166MHz. The PLL reduces the access time (ta) for the DDR. ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits RCLK REN t ERCLK ERCLK ERCLK EREN QOUT (PLL on) EF PAE NOTES single-ended clocking scheme, ERCLK is 50% duty cycle. 2. QOUT ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits STANDARD MODE OPERATION WRITE QUEUE SELECTION AND WRITE OPERATION (STANDARD MODE) The IDT72P51767/72P51777 multi-queue flow-control devices can be configured maximum of 128 ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits READ QUEUE SELECTION AND READ OPERATION (STANDARD MODE) The IDT72P51767/72P51777 multi-queue flow-control devices can be configured maximum of 128 queues which data ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits SWITCHING QUEUES ON THE WRITE PORT The IDT72P51767/72P51777 multi-queue flow-control devices can be configured maximum of 128 queues. Data is written into ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits The IDT72P51767/72P51777 multi-queue flow-control device supports writing and reading from either the same queue of from different queues. The device also supports simultaneous queue switching ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits OUTPUT DATA DURING A QUEUE SWITCH REN REN (internal) RCLK Qout EREN During this cycle the 10G MQ device detects the assertion of REN NOTE: ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits REN RCLK Qout EREN During this cycle the 10G MQ device detects the assertion of REN Figure 15. Output Data during a Queue Switch (SDR ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits Parameters: SDR Mode, PLL=ON, 1 read operation, centered aligned data/clock pause, 1 word read operation REN RCLK Qout EREN During this cycle the 10G MQ ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits Parameters: DDR Mode, PLL=ON, 1 word read operation, centered aligned data/clock pause with No queue switch, 1 word read operation REN RCLK Qout EREN During ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits Parameters: DDR Mode, PLL=OFF, 1 word read operation, edge aligned data/clock pause with No queue switch, 1 word read operation REN RCLK Qout EREN During ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits Parameters: DDR Mode, PLL=ON, 2 word read operation, WITH QUEUE SWITCH to NQ and QUEUE SWITCH BACK TO ORIGINAL QUEUE, 2 word read operation REN ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits Parameters: SDR Mode, PLL=OFF, 3 word read operation, edge aligned data/clock, pause with No queue switch. REN RCLK -2 Qout EREN During this cycle the ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits TABLE 11 — BACKUP USAGE WHEN RE-ENTERING A QUEUE Operating Mode of Frequency Operation Range 1Mhz to 166Mhz SDR PLL=OFF 1Mhz to 166Mhz SDR PLL=OFF ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits SWITCHING QUEUES ON THE READ PORT The IDT72P51767/72P51777 multi-queue flow-control devices can be configured maximum of 128 queues. Data is read from ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits SIMULTANEOUS QUEUE SWITCHING The IDT72P51767/72P51777 multi-queue flow-control device supports reading and writing from either the same queue or from different queues. The device also supports ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits QUEUE MARKing The overall intent of the MARK function is to provide the ability to either re- write and/or re-read information that is stored into ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits Write Queue MARK WCLK WADEN WADEN Read Queue MARK RCLK RADEN RADEN MARK Operational Notes: Write Port - MARKing ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits Un-MARKing a Queue UN-MARKing a Queue Write Queue UN-MARK WCLK WADEN WADEN A 1 Read Queue UN-MARK RCLK RADEN RADEN A 1 UN-MARK Operational Notes: ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits Leaving a MARK Active During a Queue switch the value of WEN for the write port and REN for the read port determines whether the ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits Inactivating a MARK During a Queue switch the value of WEN for the write port and REN for the read port determines whether the MARK ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits Write Cycle Action (active LOW) NO Operation Selects a Queue NO Operation NO Operation Read Cycle Action (active LOW) NO Operation Selects a Queue NO ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits FLAG DESCRIPTION PAFn FLAG BUS OPERATION The IDT72P51767/72P51777 multi-queue flow-control device can be configured for up to 128 queues, each queue having its own almost ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits ALMOST FULL FLAG As previously mentioned the multi-queue flow-control device provides a single Programmable Almost Full flag output, PAF. The PAF flag output provides a ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits ‘x’, then there may be an extra WCLK cycle delay before that queues status is correctly shown on the respective output of the PAFn bus. ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits TABLE 14 — FLAG OPERATION BOUNDARIES & TIMING Empty Flag, EF Flag Boundary I/O Set-Up EF Goes HIGH after 1 In40 to out40 (Almost Empty ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits TABLE 14 — FLAG OPERATION BOUNDARIES & TIMING (CONTINUED) Programmable Almost Empty Flag, PAE Boundary I/O Set-Up in40 to out40 (Both ports selected for same ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits TABLE 15 — INTERFACE DATA RATES Input Interface SDR SDR DDR DDR INPUT INTERFACE The input port will support either Edge Aligned data clocking or ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits BUS MATCHING OPERATION Bus Matching operation between the input port and output port is available. During a master reset of the multi-queue the state of ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits BYTE ORDER ON INPUT PORT: BYTE ORDER ON OUTPUT PORT: BYTE ORDER ON INPUT PORT: BYTE ORDER ON OUTPUT PORT: NOTES: 1. Please refer to ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits MRS t RSS WEN REN t RSS SENI t RSS FSTR, ESTR t RSS WADEN, RADEN t RSS ID0, ID1, ID2 t RSS BM[3:0] t ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits COMMERCIAL AND INDUSTRIAL 61 TEMPERATURE RANGES FEBRUARY 11, 2009 ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits COMMERCIAL AND INDUSTRIAL 62 TEMPERATURE RANGES FEBRUARY 11, 2009 ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits Master Reset Default Mode DFM = 0 MRS DFM MQ1 SENI SENO Serial Enable Serial Input SI SO SCLK Serial Clock Figure 40. Serial Port ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits COMMERCIAL AND INDUSTRIAL 64 TEMPERATURE RANGES FEBRUARY 11, 2009 ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits COMMERCIAL AND INDUSTRIAL 65 TEMPERATURE RANGES FEBRUARY 11, 2009 ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits COMMERCIAL AND INDUSTRIAL 66 TEMPERATURE RANGES FEBRUARY 11, 2009 ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits COMMERCIAL AND INDUSTRIAL 67 TEMPERATURE RANGES FEBRUARY 11, 2009 ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits COMMERCIAL AND INDUSTRIAL 68 TEMPERATURE RANGES FEBRUARY 11, 2009 ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits COMMERCIAL AND INDUSTRIAL 69 TEMPERATURE RANGES FEBRUARY 11, 2009 ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits *A* *B* RCLK t REN RCS t AH RDADD RADEN t A Q[39: RAE PAE NOTES: 1. ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits COMMERCIAL AND INDUSTRIAL 71 TEMPERATURE RANGES FEBRUARY 11, 2009 ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits COMMERCIAL AND INDUSTRIAL 72 TEMPERATURE RANGES FEBRUARY 11, 2009 ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits COMMERCIAL AND INDUSTRIAL 73 TEMPERATURE RANGES FEBRUARY 11, 2009 ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits COMMERCIAL AND INDUSTRIAL 74 TEMPERATURE RANGES FEBRUARY 11, 2009 ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits *A* *B* *C* WCLK WEN WRADD WADEN Din PAF HIGH-Z (Device 1) PAF ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits t t CLKH CLKL WCLK t t ENS ENH WEN n+1 words in Queue PAE t SKEW2 RCLK REN NOTE: 1. The waveform here shows ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits RCLK Device 1 Status Word 2 RDADD 001xxx10 t t STS STH ESTR PAEn t t ENS ENH RADEN NOTES: 1. ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits *A* *B* 1 WCLK WADEN FSTR t ENS WEN WRADD D5Q24 101 11000 Wp+1 ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits *A* *B* RCLK RADEN ESTR REN RDADD D0Q31 000 11111 OE t OLZ Qout W X WCLK ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits COMMERCIAL AND INDUSTRIAL 80 TEMPERATURE RANGES FEBRUARY 11, 2009 ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits VCC GND GND GND VCC GND GND GND NOTE: 1. ID2 MUST be unique between the devices. Figure 61. Connecting two 10G MQ 128Q devices ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits Figure 62. Connecting THREE or more 10G MQ 128Q in Expansion Mode Using WADDR bit 7/RDADD bit 7 SENI SI FXI EXI SCLK WCLK RCLK ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits JTAG INTERFACE Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to support the JTAG boundary scan interface. The IDT72P51767/72P51777 incorporates the necessary ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits 1 0 Input = TMS NOTES: 1. Five consecutive TCK cycles with TMS = 1 will reset the TAP. 2. TAP controller does not automatically ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits THE INSTRUCTION REGISTER The Instruction register allows an instruction to be shifted in serially into the processor at the rising edge of TCLK. The Instruction ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits HIGH-IMPEDANCE The optional High-Impedance instruction sets all outputs (including two-state as well as three-state types disabled (high-impedance) state and selects ...

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IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES (128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits t 1 TCK t 3 TDI/ TMS t TDO t 6 TRST t 5 SYSTEM INTERFACE PARAMETERS Parameter Symbol Test Conditions Data Output t DO ...

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ORDERING INFORMATION XXXXX X XX Device Type Power Speed Package NOTES: 1. Industrial temperature range product for the 7-5ns is available as a standard device. All other speed grades available by special order. 2. Green parts are available. For specific ...