IDT72P51777L7-5BBI IDT, Integrated Device Technology Inc, IDT72P51777L7-5BBI Datasheet - Page 12

• Manufacturer Part Number: IDT72P51777L7-5BBI
• Description: IC FLOW CTRL 40BIT 376-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72P51777L7-5BBI

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72P51777L7-5BBI

PIN DESCRIPTIONS (CONTINUED)
IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES
(128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits
OE
(R22)
PAE
(N20)
PAEn[7:0]
(PAE7-F21
PAE6-F22
PAE5-G20
PAE4-G21
PAE3-G22
PAE2-H20
PAE1-H21
PAE0-H22)
PAF
(F3)
PAFn[7:0]
(PAF7-F2
PAF6-F1
PAF5-G3
PAF4-G2
PAF3-G1
PAF2-H3
PAF1-H2
PAF0-H1)
PLL ON
(V1)
Q[39:0](Qout)
(See Pin No.
table for details)
QSEL[ 2:0]
(QSEL2-BB10
QSEL1-AA10
QSEL0-BB9)
RADEN
(T22)
RCLK
(J22)
Symbol &
Pin No.
Output Enable
Programmable
Almost-Empty
Flag
Programmable
Flag Bus
Programmable
Almost–Full Flag
Programmable
Almost-Full Flag
PLL ON
Data Output Bus
Queue Select
Read Address
Enable
Read Clock
Bus
Name
1.8V LVTTL
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
I/O TYPE
INPUT
INPUT
INPUT
INPUT
INPUT
HSTL
HSTL
HSTL
HSTL
HSTL
HSTL
HSTL
HSTL
HSTL
The Output Enable signal is the three-state control of the multi-queue data output bus Q[39:0], Qout. If a
device has been configured as a “Master” device, the Qout data outputs will be in a low impedance condition
if the OE input is LOW. If OE is HIGH then the Qout data outputs will be in high impedance. If a device is
configured a “Slave” device, then the Qout data outputs will always be in high impedance until that device
has been selected on the Read Port, at which point OE provides three-state of that respective device.
This pin provides the Almost-Empty flag status for the Queue that has been selected on the output port for
read operations, (selected via RCLK, RDADD and RADEN). This pin is LOW when the selected Queue
is almost-empty. This flag output may be duplicated on one of the PAEn bus lines. This flag is synchronized
to RCLK.
The PAEn bus is 8 bits wide. During a Master Reset this bus is setup for Almost Empty configuration. This
output bus provides PAE status of 8 queues (1 quadrant), within a selected device. During Queue read/
write operations these outputs provide programmable empty flag status or packet data available status,
in either polled or direct mode. The mode of flag operation is determined during master reset via the state
of the FM input. This flag bus is capable of High-Impedance state, this is important during expansion of
multi-queue devices. During direct operation the PAEn bus is updated to show the PAE status of a quadrant
of queues within a selected device. Selection is made using RCLK, ESTR and RDADD. During Polled
operation the PAEn bus is loaded with the PAE status of multi-queue flow-control quadrants sequentially
based on the rising edge of RCLK.
This pin provides the Almost-Full flag status for the Queue that has been selected on the input port for write
operations, (selected via WCLK, WRADD and WADEN). This pin is LOW when the selected Queue is
almost-full. This flag output may be duplicated on one of the PAFn bus lines. The PAE flag is asserted
synchronous to WCLK.
The PAFn bus is 8 bits wide. At any one time this output bus provides PAF status of 8 queues (1 quadrant),
within a selected device. During Queue read/write operations these outputs provide programmable full
flag status, in either direct or polled mode. The mode of flag operation is determined during master reset
via the state of the FM input. This flag bus is capable of High-Impedance state, this is important during
expansion of multi-queue devices. During direct operation the PAFn bus is updated to show the PAF status
of a quadrant of queues within a selected device. Selection is made using WCLK, FSTR, WRADD and
WADEN. During Polled operation the PAFn bus is loaded with the PAF status of multi-queue flow-control
quadrants sequentially based on the rising edge of WCLK.
This pin is used to enable the PLL. When PLL is activated, data will be clocked out by PLL generated clock.
These are the 40 data output pins. Data is read out of the device via these output pins on the rising edge
of RCLK provided that REN is LOW, OE is LOW and the Queue is selected. Due to bus-matching not all
outputs may be used, any unused outputs should not be connected.
The QSEL pins provides various queue programming options. Refer to Table 10, Write Queue Switch
Operation for details.
The RADEN input is used in conjunction with RCLK and the RDADD address bus to select a queue to
be read from. A queue addressed via the RDADD bus is selected on the rising edge of RCLK provided
that RADEN is HIGH. RADEN should be asserted (HIGH) only during a queue change cycle(s). RADEN
should not be permanently tied HIGH. RADEN cannot be HIGH for the same RCLK cycle as ESTR. Note,
that a read queue selection cannot be made, (RADEN must NOT go active) until programming of the part
has been completed and SENO has gone LOW.
When enabled by REN, the rising edge of RCLK reads data from the selected queue via the output bus
Qout. The queue to be read is selected via the RDADD address bus and a rising edge of RCLK while
RADEN is HIGH. A rising edge of RCLK in conjunction with ESTR and RDADD will also select the PAEn
flag quadrant to be placed on the PAEn bus during direct flag operation. During polled flag operation the
PAEn bus is cycled with respect to RCLK and the ESYNC signal is synchronized to RCLK. The PAE, and
12
Description
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 11, 2009