IDT72P51777L7-5BBI IDT, Integrated Device Technology Inc, IDT72P51777L7-5BBI Datasheet - Page 55

• Manufacturer Part Number: IDT72P51777L7-5BBI
• Description: IC FLOW CTRL 40BIT 376-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72P51777L7-5BBI

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72P51777L7-5BBI

NOTE:
1. EF Timing
Assertion:
De-assertion:
Read Operation to EF HIGH: t
2. In40 = SDR40 or DDR20
NOTE:
D = Queue Depth
m = Almost Full Offset value.
1. In40 = SDR40 or DDR20
PAF Timing
Assertion:
De-assertion: Read to PAF HIGH: t
PAFn Timing
Assertion:
De-assertion: Read to PAFn HIGH: t
* If a queue switch is occurring on the write port at the point of flag assertion or de-assertion
there may be one additional WCLK clock cycle delay.
IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES
(128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits
in40 to out40
(Both ports selected for same queue when the 1
in40 to out40
(Write port only selected for same queue when the D-m Writes
1
in40 to out20
Word is written in until the boundary is reached)
In40 to out40 (Almost Empty Mode)
(Both ports selected for same queue
when the 1
In40 to out20
(Both ports selected for same queue
when the 1
In20 to out40
(Both ports selected for same queue
when the 1
st
In20 = SDR20
Write to EF HIGH: t
If t
In20 = SDR20
Word is written in until the boundary is reached) (see note below for timing)
Programmable Almost Full Flag, PAF & PAFn Bus Boundary
SKEW1
I/O Set-Up
is violated there may be 1 added clock: t
st
st
st
Write Operation to PAF LOW: 3 WCLK + t
If t
Write Operation to PAFn LOW: 2 WCLK* + t
If t
Word is written in)
Word is written in)
Word is written in)
SKEW3
SKEW2
I/O Set-Up
SKEW1
is violated there may be 1 added clock: t
is violated there may be 1 added clock: t
Empty Flag, EF Flag Boundary
TABLE 14 — FLAG OPERATION BOUNDARIES & TIMING
+ RCLK + t
REF
SKEW2
SKEW3
ROV
+ WCLK + t
+ WCLK* + t
EF Goes HIGH after 1
(see note 1 below for timing)
EF Goes HIGH after 1
(see note 1 below for timing)
EF Goes HIGH after 1
(see note 1 below for timing)
st
EF Boundary Condition
SKEW1
WAF
PAF/PAFn Goes LOW after
D-m Writes
(see note below for timing)
PAF/PAFn Goes LOW after
PAF/PAFn Goes LOW after
D-m Writes (see below for timing)
WAF
PAF
PAF & PAFn Boundary
PAF
+ 2 RCLK + t
SKEW3
SKEW2
+ 3 WCLK* + t
+ 3 WCLK + t
st
st
st
Write
Write
Write
REF
WAF
PAF
55
(Both ports selected for same queue
NOTE:
D = Queue Depth
FF Timing
Assertion:
De-assertion:
1. In40 = SDR40 or DDR20
In40 to out40
(Both ports selected for same queue
when the 1
In40 to out40
(Write port only selected for queue
when the 1
In40 to out20
(Both ports selected for same queue
when the 1
In40 to out20
(Write port only selected for queue
when the 1
In20 to out40
when the 1
In20 to out40
(Write port only selected for queue
when the 1
Write Operation to FF LOW: t
Read to FF HIGH: t
If t
In20 = SDR20
SKEW1
I/O Set-Up
is violated there may be 1 added clock: t
st
st
st
st
st
st
Word is written in)
Word is written in)
Word is written in)
Word is written in)
Word is written in)
Word is written in)
SKEW1
+ t
Full Flag, FF Boundary
WFF
WFF
COMMERCIAL AND INDUSTRIAL
FF Goes LOW after D Writes
(see note below for timing)
FF Goes LOW after D Writes
(see note below for timing)
FF Goes LOW after D Writes
(see note below for timing)
FF Goes LOW after D Writes
(see note below for timing)
FF Goes LOW after ([D] x 2) Writes
(see note below for timing)
FF Goes LOW after (D x 2) Writes
(see note below for timing)
FF Boundary Condition
TEMPERATURE RANGES
SKEW1
FEBRUARY 11, 2009
+WCLK +t
WFF