IDT72P51777L7-5BBI IDT, Integrated Device Technology Inc, IDT72P51777L7-5BBI Datasheet - Page 9

• Manufacturer Part Number: IDT72P51777L7-5BBI
• Description: IC FLOW CTRL 40BIT 376-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72P51777L7-5BBI

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72P51777L7-5BBI

Connecting three or more 10G Multi-Queue 128Q in Expansion mode using
WRADD bit 7 / RDADD bit 7 for device connection details.
10Gbps MULTI-QUEUE DIFFERENCES FROM THE 4M MULTI-QUEUE
applications that needed 10Gb/s of bandwidth, and the flexibility of buffering
packets of information in large bursts such as Jumbo Ethernet packets that can
be as large as 9KBs. Listed below are the differences between the 10G Multi-
Queue and the previous 4M Multi-Queue with descriptions of the enhancements
made to support performance functions in queuing.
PERFORMANCE ENHANCEMENTS
IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES
(128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits
The 10G Multi-Queue was developed to support very high performance
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333.34 Mbps (per pin) High speed data rate in DDR mode
x40 Din and x40 Qout (8 more pins for user selectable operation such as
parity check or packet tagging)
Electrical compatibility to 802.3ae XGMII specification for passive
interconnection to Ethernet devices.
Burst of 2 timing and interface logic
- Single clocking in DDR and SDR, PLL on/off Mode. (PAD_PLLON
pin) allowing data latency to be the same for SDR and DDR.
- Output impedance matching for signal quality on the output pins.
- More Data latency (same cycle on write, 1 cycle on read)
TABLE 1 — SUMMARY OF THE DIFFERENCES BETWEEN
THE 4M MQ AND 10G MQ
Data Transfer Modes
Bus Width
XGMII Compatibility
Access time (ta)
Data Storage Capacity
Data Throughput
Operating Frequency
Configurable Queues
Package
Output Impedance Technology
I/O Voltages
Echo read Clock
Modes of Operation
Output data Clocking
FEATURE
4M MQ (IDT72P51769)
FWFT, IDT, Packet
1.5V,1.8V, 2.5V
256 pin PBGA
Edge aligned
x36, x18, x9
3.6 ns max
Up to 128
7.2Gbps
200mhz
SDR
4Mb
9
no
no
no
USER FLEXIBILITY IMPROVEMENTS
register until it's read.
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10Mbits of storage and queuing density for support large packet frames
such as Jumbo Ethernet
During a Queue switch, BOI mode preserves the data word in the output
Programmable Default configuration of 128, 64, 32, 16, 8 or 4 symmetrical
queues are available using DFM, QSEL[2:0] pins
User selectable I/O: 1.5V HSTL, or 1.8V eHSTL for faster switching I/O
Expansion of up to 256 queues and/or 80Mbit logical configuration using
up to 8 multi-queue devices
Default flag offset value is defined according to bus matching configuration
“Real Time” Flags, for both DDR and SDR.
- Three “echo” output pins: ERCLK, ERCLK, and EREN
used for Source Synchronous data on the output. Data can be center
aligned on the Echo Clock or issued on the rising edge of the Echo Clock.
- Access Time (Ta) reduced to 0.48ns with Echo Clock used for faster
Synchronized data delivery down stream
- PAF/PAE have 1 more cycle (WCLK/RCLK) latency (3 vs. 2)
- Tskew of EF/PAE with respect to WCLK has 1 WCLK cycle delay.
- Tskew of FF/PAF with respect to RCLK has 1 RCLK cycle delay.
- The PAE flag can be used as a packet indicator
10M MQ (IDT72P51777)
Centered aligned
376 pin BGA
0.48ns max
SDR, DDR
1.5V,1.8V
Up to 128
x40, x20
IDT, BOI
10Gbps
166mhz
10Mb
yes
yes
yes
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 11, 2009