IDT72P51777L7-5BBI IDT, Integrated Device Technology Inc, IDT72P51777L7-5BBI Datasheet - Page 56

• Manufacturer Part Number: IDT72P51777L7-5BBI
• Description: IC FLOW CTRL 40BIT 376-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72P51777L7-5BBI

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72P51777L7-5BBI

NOTE:
n = Almost Empty Offset value.
1. In40 = SDR40 or DDR20
PAE Timing
Assertion:
De-assertion: Write to PAE HIGH: t
PAEn – POLLED BUS
mode. In polled mode the PAEn bus automatically cycles through the 4 status
words within the device regardless of how many queues have been setup in
the part. Every rising edge of the RCLK causes the next status word to be loaded
on the PAEn bus. The device configured as the master (MAST input tied HIGH),
will take control of the PAEn after MRS goes LOW. For the whole RCLK cycle
that the first status word is on PAEn the ESYNC (PAEn bus sync) output will be
HIGH, for all other status words, this ESYNC output will be LOW. This ESYNC
output provides the user with a mark with which they can synchronize to the
PAEn bus, ESYNC is always HIGH for the RCLK cycle that the first status word
of a device is present on the PAEn bus.
will be set as the Master (ID='000'), MAST input tied HIGH, all other devices
will have MAST tied LOW. The master device is the first device to take control
of the PAEn bus and will place its first status word on the bus on the rising edge
of RCLK after the MRS input goes LOW. For the next n RCLK cycles (n=number
of queues divided by 8 with n incrementing by one should there be a remainder)
IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES
(128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits
in40 to out40
(Both ports selected for same queue when the 1
Word is written in until the boundary is reached)
in40 to out20
(Both ports selected for same queue when the 1
Word is written in until the boundary is reached)
in20 to out40
(Both ports selected for same queue when the 1
Word is written in until the boundary is reached)
In20 = SDR20
If FM is HIGH at master reset then the PAEn bus operates in Polled (looped)
When devices are connected in expansion configuration, only one device
TABLE 14 — FLAG OPERATION BOUNDARIES & TIMING (CONTINUED)
Programmable Almost Empty Flag, PAE Boundary
Read Operation to PAE LOW: 3 RCLK + t
If t
SKEW2
I/O Set-Up
is violated there may be 1 added clock: t
SKEW2
+ RCLK + t
st
st
st
RAE
PAE Goes HIGH after n+1
Writes
(see note below for timing)
PAE Goes HIGH after n+1
Writes
(see note below for timing)
PAE Goes HIGH after
([n+1] x 2) Writes
(see note below for timing)
RAE
PAE Assertion
SKEW2
+ 3 RCLK + t
RAE
56
NOTE:
n = Almost Empty Offset value.
1. In40 = SDR40 or DDR20
PAEn Timing
Assertion:
De-assertion: Write to PAEn HIGH: t
* If a queue switch is occurring on the read port at the point of flag assertion or de-assertion
there may be one additional RCLK clock cycle delay.
the master device will maintain control of the PAEn bus and cycle its status words
through it, all other devices hold their PAEn outputs in High-Impedance. When
the master device has cycled all of its status words it passes a token to the next
device in the chain and that device assumes control of the PAEn bus and then
cycles its status words and so on, the PAEn bus control token being passed on
from device to device. This token passing is done via the EXO outputs and EXI
inputs of the devices (“PAE Expansion Out” and “PAE Expansion In”). The EXO
output of the master device connects to the EXI of the second device in the chain
and the EXO of the second connects to the EXI of the third and so on. The final
device in a chain has its EXO connected to the EXI of the first device, so that once
the PAEn bus has cycled through all status words of all devices, control of the
PAEn will pass to the master device again and so on. The ESYNC of each
respective device will operate independently and simply indicate when that
respective device has taken control of the bus and is placing its first status word
on to the PAEn bus.
the EXO output of the same device. In single device mode a token is still required
to be passed into the device for accessing the PAEn bus.
in40 to out40
(Both ports selected for same queue when the 1
Word is written in until the boundary is reached)
in40 to out40
(Write port only selected for same queue when the n+1 Writes
1
in40 to out20
in20 to out40
(Both ports selected for same queue when the 1
Word is written in until the boundary is reached)
in20 to out40
(Write port only selected for same queue when the ([n+1] x 2) Writes
1
st
st
In20 = SDR20
When operating in single device mode the EXI input must be connected to
Word is written in until the boundary is reached) (see note below for timing)
Word is written in until the boundary is reached) (see note below for timing)
Programmable Almost Empty Flag Bus, PAEn Boundary
Read Operation to PAEn LOW: 3 RCLK* + t
If t
SKEW3
I/O Set-Up
is violated there may be 1 added clock: t
SKEW3
COMMERCIAL AND INDUSTRIAL
+ RCLK* + t
st
st
TEMPERATURE RANGES
PAEn Boundary Condition
PAEn Goes HIGH after
n+1 Writes
(see note below for timing)
PAEn Goes HIGH after
PAEn Goes HIGH after n+1
Writes (see below for timing)
PAEn Goes HIGH after
([n+1] x 2) Writes
(see note below for timing)
PAEn Goes HIGH after
PAE
FEBRUARY 11, 2009
PAE
SKEW3
+ 3 RCLK* + t
PAE