IDT72P51777L7-5BBI IDT, Integrated Device Technology Inc, IDT72P51777L7-5BBI Datasheet - Page 27

• Manufacturer Part Number: IDT72P51777L7-5BBI
• Description: IC FLOW CTRL 40BIT 376-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72P51777L7-5BBI

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72P51777L7-5BBI

DEFAULT PROGRAMMING
queue device will be configured for default programming, (serial programming
is not permitted). Default programming provides the user with a simpler,
however limited means to setup the multi-queue flow-control device, rather than
using the serial programming method. The default mode will configure a multi-
queue device with the maximum number of queues setup, and the available
memory allocated equally between the queues. The values of the PAE/PAF
offsets is determined by the state of the (default) pin during a master reset.
queues, each queue being 256 x40, 512 x40, and 1024 x40 deep respectively.
user simply has to apply WCLK cycles after a master reset, until SENO goes
LOW, this signals that default programming is complete. These clock cycles are
required for the device to load its internal setup registers. When a single multi-
queue device is used, the completion of device programming is signaled by the
SENO output of a device going from HIGH to LOW. Note, that SENI must be held
LOW when a device is setup for default programming mode.
SENI of the first device in a chain can be held LOW. The SENO of a device should
connect to the SENI of the next device in the chain. The SENO of the final device
is used to indicate that default programming of all devices is complete. When the
master (ID='000') SENO goes LOW normal operations may begin. Again, all
devices will be programmed with their maximum number of queues and the
memory divided equally between them. Please refer to Figure 38, Default
Programming.
PARALLEL PROGRAMMING
LOW then LOW to HIGH) if the DFM (Default Mode) input signal is HIGH and
the QSEL[2:0] input signal is "110" for Write address and "111" for Read
address, the Multi-Queue Flow Control device is configured for Parallel
Programming. Parallel Programming enables the number of queues within the
TABLE 6 — ID[2:0] AND WRADD[7:5]/RDADD[7:5] CONFIGURATION
IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES
(128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits
Queues Addressed
ID[2:0] Master Device Configuration
WRADD[7:5] or RDADD[7:5]
ID[2:0] 2nd Device Configuration
WRADD[7:5] or RDADD[7:5]
ID[2:0] 3rd Device Configuration
WRADD[7:5] or RDADD[7:5]
ID[2:0] 4th Device Configuration
WRADD[7:5] or RDADD[7:5]
ID[2:0] 5th Device Configuration
WRADD[7:5] or RDADD[7:5]
ID[2:0] 6th DeviceConfiguration
WRADD[7:5] or RDADD[7:5]
ID[2:0] 7th Device Configuration
WRADD[7:5] or RDADD[7:5]
ID[2:0] 8th Device Configuration
WRADD[7:5] or RDADD[7:5]
During a Master Reset if the DFM (Default Mode) input is HIGH the multi-
For the IDT72P51767/72P51777 devices the default mode will setup 128
When configuring the IDT72P51767/72P51777 devices in default mode the
When multi-queue devices are connected in expansion configuration, the
During a Master Reset cycle (i.e. the MRS signal transitions from HIGH to
x
128
0xx
1xx
NA
NA
NA
NA
NA
NA
00x
10x
01x
11x
NA
NA
NA
NA
64
27
000
100
010
110
001
101
011
111
device to be set through either the Write Address (WRADD) bus or Read
Address (RDADD) bus after the Master Reset cycle. Within Parallel Program-
ming mode the Multi-Queue (MQ) device programmable parameters are;
number of queues, queue depth, PAE/PAF flag offset value, bus matching and
the I/O voltage level. As previously indicated, the number of queues are
configured using the write or read address bus, however bus matching is set
during the Master Reset cycle. The value that is set during the Master Reset
cycle is determined by the Bus Matching (BM) bits. For the IDT72P51767/
72P51777 devices in Parallel Programming Mode the value of the PAE/PAF
offsets at master reset is determined by the state of the input.
gramming Mode the user simply has to apply WCLK cycles after a master reset,
until SENO goes LOW, this signals that Parallel Programming is complete. These
clock cycles are required for the device to load its internal setup registers. When
a single multi-queue device is used, the completion of device programming is
signaled by the SENO output of a device going from HIGH to LOW. Note, that
SENI must be held LOW when a device is setup for Parallel Programming mode.
ID[2:0] PINS AND WRADD/RDADD CONFIGURATIONS
of 256 Queues by 2 to 8 devices depending on the configuration setup. For
programming the ID Codes for each device the WRADD/RDADD address
buses impose the limitation of 256 Queues because, with an 8-bit address bus,
the 3 MSB in the WRADD/RDADD are used to decode the ID[2:0] pins on each
device. The slave devices must be configured before the master device as well.
For 8-device expansion the least [4:0] bits are used for expansion addressing
meaning a configuration of 32 queues can be accomplished. The MSBs [7:5]
will select which of the eight devices to access depending on their MSB ID[2:0]
settings. If ID[2:0] is 000, then it serves as the master device. Otherwise, the
devices will serve as the slave devices. Ex: For using two 128 queue MQ
devices, ID[2:0] = 0xx is for selecting the master device. For using 8 devices,
ID[2:0] = 111 is for selecting the 8th slave device and WRADD/RDADD bits [4:0]
for configuring 32 queues/device. And so on.
32
When configuring the IDT72P51767/72P51777 devices in Parallel Pro-
The 10G DDR Multi-Queue will have the ability to expand up to a maximum
000
100
010
110
001
101
011
111
16
000
100
010
110
001
101
011
111
8
000
100
010
110
001
101
011
111
4
COMMERCIAL AND INDUSTRIAL
000
100
010
110
001
101
011
111
2
TEMPERATURE RANGES
FEBRUARY 11, 2009