ADC1415S125/DB,598 NXP Semiconductors, ADC1415S125/DB,598 Datasheet
ADC1415S125/DB,598
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ADC1415S series Single 14-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps with input buffer; CMOS or LVDS DDR digital outputs Rev. 4 — 17 December 2010 1. General description The ADC1415S is a single channel 14-bit Analog-to-Digital ...
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... NXP Semiconductors 3. Applications Wireless and wired broadband communications Portable instrumentation Imaging systems Digital predistortion loop, power amplifier linearization 4. Ordering information Table 1. Ordering information Type number f (Msps) Package s ADC1415S125HN/C1 125 ADC1415S105HN/C1 105 ADC1415S080HN/C1 80 ADC1415S065HN/C1 65 ADC1415S_SER Product data sheet Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs ...
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... NXP Semiconductors 5. Block diagram INP INM Fig 1. ADC1415S_SER Product data sheet Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs ADC1415S CORRECTION AND S/H INPUT INPUT BUFFER STAGE STAGE AND DUTY CYCLE CONTROL Block diagram All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning terminal 1 index area 1 REFB REFT 2 AGND 3 VCM 4 5 VDDA5V ADC1415S 6 AGND HVQFN40 INM 7 INP 8 AGND 9 10 VDDA3V Transparent top view Fig 2. Pin configuration with CMOS digital outputs selected 6.2 Pin description Table 2. Symbol REFB REFT ...
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... NXP Semiconductors Table 2. Symbol D13 D12 D11 D10 DAV n.c. VDDO OGND OTR SCLK/DFS SDIO/ODS CS SENSE VREF [1] P: power supply; G: ground; I: input; O: output; I/O: input/output. Table 3. Symbol D12_D13_M 17 D12_D13_P D10_D11_M D10_D11_P D8_D9_M D8_D9_P D6_D7_M D6_D7_P D4_D5_M D4_D5_P D2_D3_M D2_D3_P D0_D1_M ADC1415S_SER Product data sheet Single 14-bit ADC ...
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... NXP Semiconductors Table 3. Symbol D0_D1_P DAVM DAVP [1] Pins and pins are the same for both CMOS and LVDS DDR outputs (see [2] P: power supply; G: ground; I: input; O: output; I/O: input/output. 7. Limiting values Table 4. In accordance with the Absolute Maximum Rating System (IEC 60134). ...
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... NXP Semiconductors 9. Static characteristics Table 6. Static characteristics Symbol Parameter Supplies V analog supply voltage 5 V DDA(5V) V analog supply voltage 3 V DDA(3V) V output supply voltage DDO I analog supply current 5 V DDA(5V) I analog supply current 3 V DDA(3V) I output supply current DDO P power dissipation Clock inputs: pins CLKP and CLKM ...
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... NXP Semiconductors Table 6. Static characteristics Symbol Parameter I LOW-level input current IL I HIGH-level input current IH C input capacitance I Digital outputs, CMOS mode: pins D13 to D0, OTR, DAV Output levels DDO V LOW-level output voltage OL V HIGH-level output voltage OH C output capacitance O Output levels ...
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... NXP Semiconductors Table 6. Static characteristics Symbol Parameter Accuracy INL integral non-linearity DNL differential non-linearity E offset error offset E gain error G Supply PSRR power supply rejection ratio [1] Typical values measured at V DDA(3V) are across the full temperature range T internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified. ...
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Dynamic characteristics 10.1 Dynamic characteristics [1] Table 7. Dynamic characteristics Symbol Parameter Conditions Analog signal processing α second MHz 2H i harmonic level MHz MHz 170 ...
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Table 7. Dynamic characteristics …continued Symbol Parameter Conditions IMD Intermodul MHz i ation distortion MHz MHz 170 MHz i [1] Typical values measured ...
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Clock and digital output timing Table 8. Clock and digital output timing characteristics Symbol Parameter Conditions Clock timing input: pins CLKP and CLKM f clock frequency clk t data latency lat(data) time δ clock duty cycle DCS_EN = 1 ...
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Table 8. Clock and digital output timing characteristics Symbol Parameter Conditions LVDS DDR mode timing output: pins D12_D13_P to D0_D1_P, D12_D13_M to D0_D1_M, DAVP and DAVM t propagation DATA PD delay DAV t set-up time su t hold time h ...
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... NXP Semiconductors Fig Fig 5. ADC1415S_SER Product data sheet Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs d(s) t clk CLKP CLKM − 14) DATA DAV t CMOS mode timing d(s) t clk CLKP CLKM − 14 DAVP DAVM t clk LDVS DDR mode timing All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 10.3 SPI timings Table 9. Symbol t w(SCLK) t w(SCLKH) t w(SCLKL clk(max) [1] Typical values measured at V minimum and maximum values are across the full temperature range T V DDA Fig 6. ADC1415S_SER Product data sheet Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs ...
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... NXP Semiconductors 10.4 Typical characteristics 100 SFDR (dBc ° 170 MHz (1) DCS on (2) DCS off Fig 7. Spurious-free dynamic range as a function of duty cycle (δ) 92 SFDR (dBc) (1) ( −40 °C, typical supply voltages (1) T amb = +25 °C, typical supply voltages (2) T amb = +90 °C, typical supply voltages ...
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... NXP Semiconductors 90 SFDR (dBc 0.5 1.0 1.5 2.0 Fig 11. Spurious-free dynamic range as a function of common-mode input voltage (V 11. Application information 11.1 Device control The ADC1415S can be controlled via the Serial Peripheral Interface (SPI control mode) or directly via the I/O pins (Pin control mode). ...
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... NXP Semiconductors 11.1.2 Operating mode selection The active ADC1415S operating mode (Power-up, Power-down or Sleep) can be selected via the SPI interface (see described in Table 10. Pin PWD 11.1.3 Selecting the output data standard The output data standard (CMOS or LVDS DDR) can be selected via the SPI interface ...
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... NXP Semiconductors INP INM Fig 14. Input sampling circuit and input buffer The integrated input buffer offers the following advantages: • The kickback effect is avoided - the charge injection and glitches generated by the S/H input stage are isolated from the input circuitry. So there’s no need for additional filtering. • ...
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... NXP Semiconductors 11.2.2 Transformer The configuration of the transformer circuit is determined by the input frequency. The configuration shown in Fig 15. Single transformer configuration suitable for baseband applications The configuration shown in both cases, the choice of transformer is a compromise between cost and performance. Fig 16. Dual transformer configuration suitable for high intermediate frequency ...
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... NXP Semiconductors 11.3 System reference and power management 11.3.1 Internal/external references The ADC1415S has a stable and accurate built-in internal reference voltage to adjust the ADC full-scale. This reference voltage can be set internally via SPI or with pins VREF and SENSE (programmable steps between 0 dB and −6 dB via control bits INTREF[2:0] when bit INTREF_EN = logic 1 ...
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... NXP Semiconductors VREF 330 pF REFERENCE EQUIVALENT SCHEMATIC SENSE Fig 18. Internal reference (p-p) full scale VREF 0.1 μF V SENSE VDDA Fig 20. External reference (p- (p-p) full-scale Figure 18 required reference voltage source. 11.3.2 Programmable full-scale The full-scale is programmable between 1 V (peak-to-peak (peak-to-peak) (see Table Table 12 ...
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... NXP Semiconductors 11.4 Clock input 11.4.1 Drive modes The ADC1415S can be driven differentially (LVPECL). It can also be driven by a single-ended Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS) signal connected to pin CLKP (pin CLKM should be connected to ground via a capacitor) or CLKM (pin CLKP should be connected to ground via a capacitor). ...
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... NXP Semiconductors 11.4.2 Equivalent input circuit The equivalent circuit of the input clock buffer is shown in voltage of the differential input stage is set via internal 5 kΩ resistors. Fig 24. Equivalent input circuit Single-ended or differential clock inputs can be selected via the SPI interface (see Table control bit SE_SEL ...
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... NXP Semiconductors 11.5 Digital outputs 11.5.1 Digital output buffers: CMOS mode The digital output buffers can be configured as CMOS by setting bit LVDS_CMOS to logic_0 (see Each digital output has a dedicated output buffer. The equivalent circuit of the CMOS digital output buffer is shown in OGND/V Each buffer can be loaded by a maximum of 10 pF. ...
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... NXP Semiconductors 11.5.2 Digital output buffers: LVDS DDR mode The digital output buffers can be configured as LVDS DDR by setting bit LVDS_CMOS to logic_1 (see Fig 26. LVDS DDR digital output buffer - externally terminated Each output should be terminated externally with a 100 Ω resistor (typical) at the receiver ...
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... NXP Semiconductors Table 13. LVDS_INT_TER[2:0] 101 110 111 11.5.3 DAta Valid (DAV) output clock A data valid output clock signal (DAV) is provided that can be used to capture the data delivered by the ADC1415S. Detailed timing diagrams for CMOS and LVDS DDR modes are provided in 11.5.4 Out-of-Range (OTR) An out-of-range signal is provided on pin OTR ...
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... NXP Semiconductors 11.5.7 Output codes versus input voltage Table 15. − INP < −1 −1 −0.9998779 −0.9997559 −0.9996338 −0.9995117 .... −0.0002441 −0.0001221 0 +0.0001221 +0.0002441 .... +0.9995117 +0.9996338 +0.9997559 +0.9998779 +1 > +1 11.6 Serial Peripheral Interface (SPI) 11.6.1 Register description The ADC1415S serial interface is a synchronous serial communications port that allows easy interfacing with many commonly-used microprocessors ...
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... NXP Semiconductors Table 17 Bits A12 to A0 indicate the address of the register being accessed. In the case of a multiple byte transfer, this address is the first register to be accessed. An address counter is increased to access subsequent addresses. The steps involved in a data transfer are as follows falling edge combination with a rising edge on SCLK determine the start of communications ...
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... NXP Semiconductors Fig 29. Default mode at start-up: SCLK LOW = offset binary; SDIO HIGH = LVDS DDR Fig 30. Default mode at start-up: SCLK HIGH = two’s complement; SDIO LOW = CMOS ADC1415S_SER Product data sheet Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs CS SDIO ...
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Register allocation map Table 18. Register allocation map Add Register name R/W Bit definition Hex Bit 7 Bit 6 0005 Reset and R/W SW_RST operating mode 0006 Clock R 0008 Internal reference R 0010 Input ...
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... NXP Semiconductors Table 19. Reset and operating mode control register (address 0005h) bit description Default values are highlighted. Bit Symbol Access 7 SW_RST R RESERVED[2: OP_MODE[1:0] R/W Table 20. Clock control register (address 0006h) bit description Default values are highlighted. Bit Symbol Access SE_SEL R/W ...
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... NXP Semiconductors Table 21. Internal reference control register (address 0008h) bit description Default values are highlighted. Bit Symbol Access INTREF_EN R INTREF[2:0] R/W Table 22. Input buffer control register (address 0010h) bit description Default values are highlighted. Bit Symbol IB_IBIAS[1:0] Table 23. Output data standard control register (address 0011h) bit description Default values are highlighted ...
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... NXP Semiconductors Table 23. Output data standard control register (address 0011h) bit description Default values are highlighted. Bit Symbol DATA_FORMAT[1:0] Table 24. Output clock register (address 0012h) bit description Default values are highlighted. Bit Symbol DAVINV DAVPHASE[2:0] Table 25. Offset register (address 0013h) bit description Default values are highlighted ...
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... NXP Semiconductors Table 26. Test pattern register 1 (address 0014h) bit description Default values are highlighted. Bit Symbol TESTPAT_SEL[2:0] Table 27. Test pattern register 2 (address 0015h) bit description Default values are highlighted. Bit Symbol TESTPAT_USER[13:6] Table 28. Test pattern register 3 (address 0016h) bit description Default values are highlighted. ...
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... NXP Semiconductors Table 30. CMOS output register (address 0020h) bit description Default values are highlighted. Bit Symbol Access DAV_DRV[1:0] R DATA_DRV[1:0] R/W Table 31. LVDS DDR output register 1 (address 0021h) bit description Default values are highlighted. Bit Symbol Access DAVI_x2_EN R DAVI[1:0] R/W 2 DATAI_x2_EN R/W ...
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... NXP Semiconductors Table 32. LVDS DDR output register 2 (address 0022h) bit description Default values are highlighted. Bit Symbol BIT/BYTE_WISE LVDS_INTTER[2:0] ADC1415S_SER Product data sheet Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs Access Value Description 0000 not used R/W DDR mode for LVDS output ...
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... NXP Semiconductors 12. Package outline HVQFN40: plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 0.85 mm terminal 1 index area terminal 1 40 index area Dimensions (1) Unit max 1.00 0.05 0.30 mm nom 0.85 0.02 0.21 0.2 min 0.80 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 13. Revision history Table 33. Revision history Document ID ADC1415S_SER v.4 Modifications: ADC1415S_SER v.3 ADC1415S065_080_105_125_2 20090604 ADC1415S065_080_105_125_1 20090528 ADC1415S_SER Product data sheet Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs Release date Data sheet status 20101217 Product data sheet • ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 16. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Limiting values Thermal characteristics . . . . . . . . . . . . . . . . . . 6 9 Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . 10 10.1 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 10.2 Clock and digital output timing . . . . . . . . . . . . 12 10 ...