ADC1415S125/DB,598 NXP Semiconductors, ADC1415S125/DB,598 Datasheet - Page 32

• Manufacturer Part Number: ADC1415S125/DB,598
• Description: BOARD DEMO FOR ADC1415S125
• Manufacturer: NXP Semiconductors
• Type: A/Dr

Specifications of ADC1415S125/DB,598

• Number Of Adc's: 1
• Number Of Bits: 14
• Sampling Rate (per Second): 125M
• Data Interface: Serial, SPI™
• Inputs Per Adc: 1 Differential
• Input Range: 1 ~ 2 Vpp
• Power (typ) @ Conditions: 840mW @ 125Msps
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC1415S125
• Product: Data Conversion Development Tools
• Conversion Rate: 125 MSPS
• Resolution: 14 bit
• Interface Type: SMA
• For Use With/related Products: ADC1415S125
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-5094

NXP Semiconductors
Table 19.
Default values are highlighted.
Table 20.
Default values are highlighted.
ADC1415S_SER
Product data sheet
Bit
7
6 to 4
3 to 2
1 to 0
Bit
7 to 5
4
3
2
1
0
Symbol
SW_RST
RESERVED[2:0]
-
OP_MODE[1:0]
Symbol
-
SE_SEL
DIFF_SE
-
CLKDIV
DCS_EN
Reset and operating mode control register (address 0005h) bit description
Clock control register (address 0006h) bit description
Access
R/W
R/W
Access
R/W
R/W
R/W
R/W
All information provided in this document is subject to legal disclaimers.
Value
0
1
000
00
00
01
10
11
Value
000
0
1
0
1
0
0
1
0
1
Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs
Rev. 4 — 17 December 2010
Description
reset digital section
reserved
not used
operating mode
Description
not used
single-ended clock input pin select
differential/single ended clock input select
not used
clock input divide by 2
duty cycle stabilizer
no reset
performs a reset on SPI registers
normal (Power-up)
Power-down
Sleep
normal (Power-up)
CLKM
CLKP
fully differential
single-ended
disabled
enabled
disabled
enabled
ADC1415S series
© NXP B.V. 2010. All rights reserved.
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