ADC1415S125/DB,598 NXP Semiconductors, ADC1415S125/DB,598 Datasheet - Page 27

• Manufacturer Part Number: ADC1415S125/DB,598
• Description: BOARD DEMO FOR ADC1415S125
• Manufacturer: NXP Semiconductors
• Type: A/Dr

Specifications of ADC1415S125/DB,598

• Number Of Adc's: 1
• Number Of Bits: 14
• Sampling Rate (per Second): 125M
• Data Interface: Serial, SPI™
• Inputs Per Adc: 1 Differential
• Input Range: 1 ~ 2 Vpp
• Power (typ) @ Conditions: 840mW @ 125Msps
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC1415S125
• Product: Data Conversion Development Tools
• Conversion Rate: 125 MSPS
• Resolution: 14 bit
• Interface Type: SMA
• For Use With/related Products: ADC1415S125
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-5094

NXP Semiconductors
ADC1415S_SER
Product data sheet
11.5.3 DAta Valid (DAV) output clock
11.5.4 Out-of-Range (OTR)
11.5.5 Digital offset
11.5.6 Test patterns
Table 13.
A data valid output clock signal (DAV) is provided that can be used to capture the data
delivered by the ADC1415S. Detailed timing diagrams for CMOS and LVDS DDR modes
are provided in
An out-of-range signal is provided on pin OTR. The latency of OTR is fourteen clock
cycles. The OTR response can be speeded up by enabling Fast OTR (bit
FASTOTR = logic 1; see
four clock cycles. The Fast OTR detection threshold (below full-scale) can be
programmed via bits FASTOTR_DET[2:0].
Table 14.
By default, the ADC1415S delivers output code that corresponds to the analog input.
However it is possible to add a digital offset to the output code via the SPI (bits
DIG_OFFSET[5:0]; see
For test purposes, the ADC1415S can be configured to transmit one of a number of
predefined test patterns (via bits TESTPAT_SEL[2:0]; see
can be defined by the user (TESTPAT_USER; see
when TESTPAT_SEL[2:0] = 101. The selected test pattern is transmitted regardless of the
analog input.
LVDS_INT_TER[2:0]
101
110
111
FASTOTR_DET[2:0]
000
001
010
011
100
101
110
111
LVDS DDR output register 2
Fast OTR register
Figure 4
All information provided in this document is subject to legal disclaimers.
Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs
Rev. 4 — 17 December 2010
Table
and
Table
Figure 5
25).
29). In this mode, the latency of OTR is reduced to only
respectively.
…continued
Resistor value (Ω)
100
81
60
Detection level (dB)
−20.56
−16.12
−11.02
−7.82
−5.49
−3.66
−2.14
−0.86
Table 27
ADC1415S series
Table
and
26). A custom test pattern
Table
28) and is selected
© NXP B.V. 2010. All rights reserved.
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