AD9204-20EBZ Analog Devices Inc, AD9204-20EBZ Datasheet
AD9204-20EBZ
Specifications of AD9204-20EBZ
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AD9204-20EBZ Summary of contents
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... VIN–B VIN+B CLK+ CLK– PRODUCT HIGHLIGHTS 1. The AD9204 operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1 3.3 V logic families. 2. The patented sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use ...
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... Timing Specifications .................................................................. 8 Absolute Maximum Ratings ............................................................ 9 Thermal Characteristics .............................................................. 9 ESD Caution .................................................................................. 9 Pin Configuration and Function Descriptions ........................... 10 Typical Performance Characteristics ........................................... 12 AD9204-80 .................................................................................. 12 AD9204-65 .................................................................................. 14 AD9204-40 .................................................................................. 15 AD9204-20 .................................................................................. 16 Equivalent Circuits ......................................................................... 17 Theory of Operation ...................................................................... 19 ADC Architecture ...................................................................... 19 Analog Input Considerations .................................................... 19 REVISION HISTORY 7/09—Revision 0: Initial Version Voltage Reference ....................................................................... 22 Clock Input Considerations ...................................................... 23 Power Dissipation and Standby Mode ...
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... GENERAL DESCRIPTION The AD9204 is a monolithic, dual-channel, 1.8 V supply, 10-bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and on-chip voltage reference. The product uses multistage differential pipeline architecture with output error correction logic to provide 10-bit accuracy at 80 MSPS data rates and to guarantee no missing codes over the full operating temperature range ...
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... Rev Page AD9204-80 Typ Max Min Typ Max 10 Guaranteed ±0.1 ±0.50 ±0.1 ±0.70 +1.8 +1.8 ±0.30 ±0.30 ±0.15 ±0.11 ±0.60 ±0.60 ±0.25 ± ...
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... Full 25°C 25°C −82 25°C −82 Full −71 25°C −82 Full 25°C 25°C Full −100 25°C 700 Rev Page AD9204 AD9204-65 AD9204-80 Typ Max Min Typ Max 61.5 61.3 61.4 61.3 61.4 61.3 60.4 61.0 61.0 61.2 61.1 61.2 61.1 61.2 61 ...
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... High Level Output Voltage μA OH High Level Output Voltage 0 Low Level Output Voltage 1 Low Level Output Voltage μ Internal 30 kΩ pull-down. 2 Internal 30 kΩ pull-up. AD9204-20/AD9204-40/AD9204-65/AD9204-80 Temp Min Full Full 0.2 Full GND − 0.3 Full −10 Full −10 Full 8 Full 1 Full 1 ...
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... Figure 3. CMOS Interleaved Output Timing Rev Page AD9204-65 AD9204-80 Min Typ Max Min Typ 625 15.38 12.5 7.69 6.25 1.0 1.0 0.1 0 0.1 0 350 350 300 260 – – – – – – – – 5 AD9204 Max Unit 625 MHz 80 MSPS rms Cycles μs ns Cycles ...
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... AD9204 TIMING SPECIFICATIONS Table 5. Parameter Conditions SYNC TIMING REQUIREMENTS t SYNC to rising edge of CLK setup time SSYNC t SYNC to rising edge of CLK hold time HSYNC SPI TIMING REQUIREMENTS t Setup time between the data and the rising edge of SCLK DS t Hold time between the data and the rising edge of SCLK ...
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... ESD CAUTION Rev Page Airflow Velocity (m/sec) θ θ 2.0 1 specified for a 4-layer PCB with a solid ground addition, metal in direct contact with the AD9204 1, 4 θ Unit JB °C/W 12 °C/W °C/W ...
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... CSB 47 OEB 48 PDWN CLK+ 1 PIN 1 CLK– 2 INDICATOR SYNC AD9204 TOP VIEW 10 (Not to Scale) 11 D1B 12 D2B 13 D3B 14 D4B 15 D5B 16 Figure 5. Pin Configuration Description Exposed paddle is the only ground connection for the chip. Must be connected to PCB AGND. Differential Encode Clock. PECL, LVDS, or 1.8 V CMOS inputs. ...
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... VIN−B, VIN+B Description 1.8 V Analog Supply Pins. Channel A Analog Inputs. Voltage Reference Input/Output. Reference Mode Selection. Analog output voltage at midsupply to set common mode of the analog inputs. Sets Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground. Channel B Analog Inputs. Rev Page AD9204 ...
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... MHz IN 2F1 – F2 –110 32.5 MHz Figure 11. AD9204-80 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with IN2 Rev Page 80MSPS 30.5MHz @ –1dBFS SNR = 60.5dB (61.5dBFS) SFDR = 83.5dBc FREQUENCY (MHz) Figure 9. AD9204-80 Single-Tone FFT with f = 30.5 MHz ...
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... Figure 12. AD9204-80 SNR/SFDR vs. Input Frequency (AIN) with 2 V p-p Full Scale 85 SFDR (dBc SNR (dBFS SAMPLE RATE (MHz) Figure 13. AD9204-80 SNR/SFDR vs. Sample Rate with AIN = 9.7 MHz 0.20 0.16 0.12 0.08 0.04 0 –0.04 –0.08 –0.12 –0.16 –0.20 24 224 424 624 OUTPUT CODE Figure 14 ...
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... FREQUENCY (MHz) Figure 20. AD9204-65 Single-Tone FFT with f –10 –30 –50 –70 –90 –110 – 9.7 MHz Figure 21. AD9204-65 SNR/SFDR vs. Input Amplitude (AIN) with 70.3 MHz Figure 22. AD9204-65 SNR/SFDR vs. Input Frequency (AIN) with 30.5 MHz IN Rev Page SFDR (dBc) ...
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... FREQUENCY (MHz) Figure 24. AD9204-40 Single-Tone FFT with 9.7 MHz Figure 25. AD9204-40 SNR/SFDR vs. Input Amplitude (AIN) with 30.5 MHz IN Rev Page SFDRFS SNRFS SFDR SNR 0 –60 –50 –40 –30 –20 INPUT AMPLITUDE (dBc) AD9204 – 9.7 MHz IN ...
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... FREQUENCY (MHz) Figure 27. AD9204-20 Single-Tone FFT with –60 = 9.7 MHz Figure 28. AD9204-20 SNR/SFDR vs. Input Amplitude (AIN) with 30.5 MHz IN Rev Page SFDR (dBFS) SNR (dBFS) SFDR (dBc) SNR (dBc) –10 –50 –40 –30 –20 INPUT AMPLITUDE (dBc 9.7MHz ...
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... Figure 31. Equivalent SDIO/DCS Input Circuit 0.9V Figure 33. Equivalent SCLK/DFS, SYNC, OEB, and PDWN Input Circuit Rev Page DRVDD Figure 32. Equivalent Digital Output Circuit DRVDD 350Ω SCLK/DFS, SYNC, OEB, AND PDWN 30kΩ AVDD 375Ω RBIAS AND VCM Figure 34. Equivalent RBIAS, VCM Circuit AD9204 ...
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... AD9204 DRVDD AVDD 30kΩ 350Ω CSB Figure 35. Equivalent CSB Input Circuit AVDD 375Ω SENSE Figure 36. Equivalent SENSE Circuit VREF Figure 37. Equivalent VREF Circuit Rev Page AVDD 375Ω 7.5kΩ ...
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... ADC performance. Operation to 300 MHz analog input is permitted but occurs at the expense of increased ADC noise and distortion. In nondiversity applications, the AD9204 can be used as a base- band or direct downconversion receiver, where one ADC is used for I input data and the other is used for Q input data. ...
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... ADC. The output common-mode voltage of the ADA4938-2 is easily set with the VCM pin of the AD9204 (see Figure 41), and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. ...
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... Figure 45. Differential Input Configuration Using the AD8352 Rev Page 10µF AVDD 1kΩ R VIN+x 0.1µF 49.9Ω 1kΩ AVDD C 1kΩ R VIN–x 10µF 0.1µF 1kΩ Figure 43. Single-Ended Input Configuration R VIN+x ADC C R VCM VIN–x R VIN+x ADC C R VCM VIN–x 0.1µF AD9204 ADC ...
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... ADC can be varied by configuring SPI Address 0x18 as shown in Table 11, resulting in a selectable differential span from p-p. If the internal reference of the AD9204 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 47 shows how the internal reference voltage is affected by loading ...
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... Jitter Considerations section. Figure 50 and Figure 51 show two preferred methods for clocking the AD9204 (at clock rates up to 625 MHz). A low jitter clock source is converted from a single-ended signal to a differential signal using either an RF transformer balun. ...
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... CLK+ performance characteristics. ADC 100Ω The AD9204 contains a duty cycle stabilizer (DCS) that retimes 0.1µF the nonsampling (falling) edge, providing an internal clock CLK– signal with a nominal 50% duty cycle. This allows the user to provide a wide range of clock input duty cycles without affecting the performance of the AD9204 ...
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... Figure 56. SNR vs. Input Frequency and Jitter The clock input should be treated as an analog signal in cases in which aperture jitter may affect the dynamic range of the AD9204. To avoid modulating the clock signal with digital noise, keep power supplies for clock drivers separate from the ADC output driver supplies ...
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... Minimize the length of the output data lines and loads placed on them to reduce transients within the AD9204. These transients can degrade converter dynamic performance. The lowest typical conversion rate of the AD9204 is 3 MSPS. At clock rates below 3 MSPS, dynamic performance can degrade. Data Clock Output (DCO) The AD9204 provides two data clock output (DCO) signals intended for capturing the data in an external register ...
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... AD9204. BUILT-IN SELF-TEST (BIST) The BIST is a thorough test of the digital portion of the selected AD9204 signal path. Perform the BIST test after a reset to ensure that the part known state. During BIST, data from an internal pseudorandom noise (PN) source is driven through the digital datapath of both channels, starting at the ADC block output ...
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... AD9204 CHANNEL/CHIP SYNCHRONIZATION The AD9204 has a SYNC input that offers the user flexible synchronization options for synchronizing sample clocks across multiple ADCs. The input clock divider can be enabled to synchronize on a single occurrence of the SYNC signal or on every occurrence. The SYNC input is internally synchronized to the sample clock ...
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... SERIAL PORT INTERFACE (SPI) The AD9204 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port ...
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... The pins described in Table 14 constitute the physical interface between the programming device of the user and the serial port of the AD9204. The SCLK and CSB pins function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback ...
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... SPI map (for example, Address 0x13) and should not be written. DEFAULT VALUES After the AD9204 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table (see Table 17). ...
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... Chip Configuration Registers 0x00 SPI port 0 LSB configuration first (global) 0x01 Chip ID (global) 8-bit chip ID bits [7:0] AD9204 = 0x25 0x02 Chip grade Open Speed grade ID 6:4 (global) 20 MSPS = 000 40 MSPS = 001 65 MSPS = 010 80 MSPS = 011 Device Index and Transfer Registers 0x05 ...
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... V p-p 010 = 1.33 V p-p 011 = 1.60 V p-p 100 = 2 B13 B12 B11 B10 Rev Page AD9204 Default Bit 0 Value Bit 1 (LSB) (Hex) Comments 0x00 When set, the test data is placed on the output pins in place of normal data Open BIST 0x00 ...
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... AD9204 Addr Register Bit 7 (Hex) Name (MSB) Bit 6 0x1C USER_PATT2_MSB B15 B14 0x24 MISR_LSB Open Open 0x2A Features Open Open 0x2E Output assign Open Open Digital Feature Control 0x10 Sync control Open Open 0 (global) 0x10 USR2 Enable Open 1 OEB Pin 47 (local) ...
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... The VCM pin should be decoupled to ground with a 0.1 μF capacitor, as shown in Figure 42. RBIAS The AD9204 requires that a 10 kΩ resistor be placed between the RBIAS pin and ground. This resistor sets the master current reference of the ADC core and should have at least a 1% tolerance. ...
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... AD9204-80EBZ 1 AD9204-65EBZ 1 AD9204-40EBZ 1 AD9204-20EBZ RoHS Compliant Part. 2 The exposed paddle (Pin 0) is the only GND connection on the chip and must be connected to the PCB AGND. ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. ...