AD9204-20EBZ Analog Devices Inc, AD9204-20EBZ Datasheet - Page 23

• Manufacturer Part Number: AD9204-20EBZ
• Description: BOARD EVALUATION 20MSPS AD9204
• Manufacturer: Analog Devices Inc

Specifications of AD9204-20EBZ

• Number Of Adc's: 2
• Number Of Bits: 10
• Sampling Rate (per Second): 20M
• Data Interface: Serial, SPI™
• Inputs Per Adc: 1 Differential
• Input Range: 1 ~ 2 Vpp
• Power (typ) @ Conditions: *
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9204
• Silicon Manufacturer: Analog Devices
• Application Sub Type: ADC
• Kit Application Type: Data Converter
• Silicon Core Number: AD9204
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Development Tool Type: Hardware / Software - Starter Kit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift charac-
teristics. Figure 48 shows the typical drift characteristics of the
internal reference in 1.0 V mode.
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7.5 kΩ load (see Figure 37). The internal buffer generates the
positive and negative full-scale references for the ADC core.
Therefore, the external reference must be limited to a maximum
of 1.0 V.
CLOCK INPUT CONSIDERATIONS
For optimum performance, clock the AD9204 sample clock
inputs, CLK+ and CLK−, with a differential signal. The signal
is typically ac-coupled into the CLK+ and CLK− pins via a
transformer or capacitors. These pins are biased internally
(see Figure 49) and require no external bias.
–1
–2
–3
–4
–5
–6
CLK+
4
3
2
1
0
–40
Figure 49. Equivalent Clock Input Circuit
–20
2pF
Figure 48. Typical VREF Drift
0
V
REF
TEMPERATURE (°C)
AVDD
ERROR (mV)
0.9V
20
40
60
2pF
CLK–
80
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Clock Input Options
The AD9204 has a very flexible clock input structure. The clock
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, clock source jitter
is of the most concern, as described in the Jitter Considerations
section.
Figure 50 and Figure 51 show two preferred methods for clocking
the AD9204 (at clock rates up to 625 MHz). A low jitter clock
source is converted from a single-ended signal to a differential
signal using either an RF transformer or an RF balun.
The RF balun configuration is recommended for clock frequencies
between 125 MHz and 625 MHz, and the RF transformer is recom-
mended for clock frequencies from 10 MHz to 200 MHz. The
back-to-back Schottky diodes across the transformer/balun
secondary limit clock excursions into the AD9204 to approx-
imately 0.8 V p-p differential.
This limit helps prevent the large voltage swings of the clock
from feeding through to other portions of the AD9204 while
preserving the fast rise and fall times of the signal that are critical
to a low jitter performance.
CLOCK
INPUT
CLOCK
INPUT
Figure 50. Transformer-Coupled Differential Clock (Up to 200 MHz)
Figure 51. Balun-Coupled Differential Clock (Up to 625 MHz)
50Ω
0.1µF
50Ω
1nF
1nF
100Ω
ADT1-1WT, 1:1 Z
Mini-Circuits
XFMR
0.1µF
®
0.1µF
0.1µF
0.1µF
0.1µF
SCHOTTKY
SCHOTTKY
HSMS2822
HSMS2822
DIODES:
DIODES:
CLK+
CLK–
CLK+
CLK–
AD9204
ADC
ADC