CDB5532U Cirrus Logic Inc, CDB5532U Datasheet - Page 25

• Manufacturer Part Number: CDB5532U
• Description: BOARD EVAL FOR CS5532U ADC
• Manufacturer: Cirrus Logic Inc

Specifications of CDB5532U

• Number Of Adc's: 2
• Number Of Bits: 24
• Sampling Rate (per Second): 3.84k
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: ±2.5 V
• Power (typ) @ Conditions: 35mW @ 3.84kSPS
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: CS5532
• Description/function: Audio DSPs
• Operating Supply Voltage: 5 V
• Product: Audio Modules
• For Use With/related Products: C8051F320
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1159

from VA+ and VA-. Their output voltage will be
limited to the VA+ voltage for a logic 1 and VA-
for a logic 0.
2.3.7. Offset and Gain Select
The Offset and Gain Select bit (OGS) is used to se-
lect the source of the calibration registers to use
when performing conversions and calibrations.
When the OGS bit is set to ‘0’, the offset and gain
registers corresponding to the desired physical
channel (CS1-CS0 in the selected Setup) will be ac-
cessed. When the OGS bit is set to ‘1’, the offset
and gain registers pointed to by the OG1-OG0 bits
in the selected Setup will be accessed. This feature
allows multiple calibration values (e.g. for different
gain settings) to be used on a single physical chan-
nel without having to re-calibrate or manipulate the
calibration registers.
DS755F3
Figure 9. Input Reference Model when VRS = 1
V
i = fV
n
os
VREF
≤ 8 mV
os
C
VRS = 1; 1 V ≤ V
f =
MCLK
16
φ Coarse
2
φ Fine
C = 14pF
1
REF
≤ 2.5 V
2.3.8. Filter Rate Select
The Filter Rate Select bit (FRS) modifies the output
word rates of the converter to allow either 50 Hz or
60 Hz
4.9152 MHz crystal. If FRS is cleared to logic 0,
the word rates and corresponding filter characteris-
tics can be selected (using the Channel Setup Reg-
isters) from 7.5, 15, 30, 60, 120, 240, 480, 960,
1920, or 3840 Sps when using a 4.9152 MHz clock.
If FRS is set to logic 1, the word rates and corre-
sponding filter characteristics scale by a factor of
5/6, making the selectable word rates 6.25, 12.5,
25, 50, 100, 200, 400, 800, 1600, and 3200 Sps
when using a 4.9152 MHz clock. When using other
clock frequencies, these selectable word rates will
scale linearly with the clock frequency that is used.
Figure 10. Input Reference Model when VRS = 0
V
i = fV
n
os
VREF
≤ 16 mV
rejection
os
C
VRS = 0; 2.5 V < V
f =
MCLK
16
when
φ Coarse
2
φ Fine
C = 7 pF
CS5532/34-BS
1
operating
REF
≤ VA+
from
25
a