CDB5532U Cirrus Logic Inc, CDB5532U Datasheet - Page 26

• Manufacturer Part Number: CDB5532U
• Description: BOARD EVAL FOR CS5532U ADC
• Manufacturer: Cirrus Logic Inc

Specifications of CDB5532U

• Number Of Adc's: 2
• Number Of Bits: 24
• Sampling Rate (per Second): 3.84k
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: ±2.5 V
• Power (typ) @ Conditions: 35mW @ 3.84kSPS
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: CS5532
• Description/function: Audio DSPs
• Operating Supply Voltage: 5 V
• Product: Audio Modules
• For Use With/related Products: C8051F320
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1159

2.3.9. Configuration Register Descriptions
26
D31(MSB) D30
PSS
D15
NU
PSS (Power Save Select)[31]
PDW (Power Down Mode)[30]
RS (Reset System)[29]
RV (Reset Valid)[28]
IS (Input Short)[27]
GB (Guard Signal Bit)[26]
VRS (Voltage Reference Select)[25]
A1-A0 (Output Latch bits)[24:23]
Output Latch Select, OLS[22]
NU (Not Used)[21]
Offset and Gain Select OGS[20]
0
1
0
1
0
1
0
1
0
1
0
1
0
1
00
01
10
11
0
1
0
0
1
PDW
D14
NU
D29
D13
RS
NU
Standby Mode (Oscillator active, allows quick power-up).
Sleep Mode (Oscillator inactive).
Normal Mode
Activate the power save select mode.
Normal Operation.
Activate a Reset cycle. See System Reset Sequence in the datasheet text.
Normal Operation
System was reset. This bit is read only. Bit is cleared to logic zero after the configuration register is read.
Normal Input
All signal input pairs for each channel are disconnected from the pins and shorted internally.
Normal Operation of A0 as an output latch.
A0’s output is modified to output the common mode output voltage of the instrumentation amplifier (typically
2.5 V). The output latch select bit is ignored when the guard buffer is activated.
2.5 V < V
1 V ≤ V
The latch bits (A0 and A1) will be set to the logic state of these bits upon command word execution if the output
latch select bit (OLS) is set. Note that these logic outputs are powered from VA+ and VA-.
A0 = 0, A1 = 0
A0 = 0, A1 = 1
A0 = 1, A1 = 0
A0 = 1, A1 = 1
When low, uses the Channel-Setup Register as the source of A1 and A0.
When set, uses the Configuration Register as the source of A1 and A0.
Must always be logic 0. Reserved for future upgrades.
Calibration registers used are based on the CS1-CS0 bits of the referenced Setup.
Calibration registers used are based on the OG1-OG0 bits of the referenced Setup.
D28
D12
NU
RV
REF
REF
≤ 2.5V
D27
D11
≤ [(VA+) - (VA-)]
NU
IS
D26
D10
GB
NU
VRS
D25
NU
D9
D24
NU
D8
A1
D23
NU
D7
A0
OLS
D22
NU
D6
D21
NU
NU
D5
OGS
D20
NU
D4
FRS
D19
NU
D3
CS5532/34-BS
D18
NU
NU
D2
D17
NU
NU
D1
DS755F3
D16
NU
NU
D0