PIC18F13K22-I/ML Microchip Technology, PIC18F13K22-I/ML Datasheet - Page 199

• Manufacturer Part Number: PIC18F13K22-I/ML
• Description: IC MCU 8BIT 8KB FLASH 20-QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F13K22-I/ML

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, MSSP, SPI, USART
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

FIGURE 15-12:
TABLE 15-8:
© 2009 Microchip Technology Inc.
BAUDCON ABDOVF
INTCON
IPR1
PIE1
PIR1
RCREG
RCSTA
SPBRG
SPBRGH
TXSTA
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
(SCKP = 0)
(SCKP = 1)
(Interrupt)
Note:
TX/CK pin
TX/CK pin
Name
CREN bit
SREN bit
bit SREN
RCIF bit
RXREG
RX/DT
Write to
Read
pin
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
‘0’
EUSART Receive Register
EUSART Baud Rate Generator Register, Low Byte
EUSART Baud Rate Generator Register, High Byte
GIE/GIEH PEIE/GIEL TMR0IE
CSRC
SPEN
Bit 7
—
—
—
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
RCIDL
ADIP
ADIE
ADIF
Bit 6
RX9
TX9
bit 0
bit 1
DTRXP
SREN
TXEN
RCIP
RCIE
RCIF
Bit 5
bit 2
CKTXP
INT0IE
Preliminary
CREN
SYNC
TXIP
TXIE
Bit 4
TXIF
PIC18F1XK22/LF1XK22
bit 3
ADDEN
SENDB
BRG16
RABIE
SSPIP
SSPIE
SSPIF
Bit 3
bit 4
TMR0IF
CCP1IP
CCP1IE
CCP1IF
BRGH
FERR
Bit 2
—
bit 5
TMR2IP
TMR2IE
TMR2IF
INT0IF
OERR
TRMT
WUE
Bit 1
bit 6
bit 7
TMR1IP
TMR1IE
TMR1IF
ABDEN
RABIF
RX9D
TX9D
Bit 0
DS41365B-page 197
on page
Values
Reset
251
249
252
252
252
251
251
251
251
251
‘0’