PIC18F13K22-I/ML Microchip Technology, PIC18F13K22-I/ML Datasheet - Page 371

• Manufacturer Part Number: PIC18F13K22-I/ML
• Description: IC MCU 8BIT 8KB FLASH 20-QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F13K22-I/ML

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, MSSP, SPI, USART
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

DCFSNZ .......................................................................... 289
DECF ............................................................................... 288
DECFSZ ........................................................................... 289
Development Support ...................................................... 319
Device Differences ........................................................... 365
Device Overview .................................................................. 7
Device Reset Timers ........................................................ 245
DEVID1 Register .............................................................. 262
DEVID2 Register .............................................................. 262
Direct Addressing ............................................................... 42
E
ECCPAS Register ............................................................ 123
EECON1 Register ........................................................ 49, 58
Effect on Standard PIC Instructions ................................. 316
Electrical Specifications ................................................... 323
Enhanced Capture/Compare/PWM (ECCP) .................... 111
Enhanced Universal Synchronous Asynchronous
Errata ................................................................................... 6
EUSART .......................................................................... 173
© 2009 Microchip Technology Inc.
Details on Individual Family Members ......................... 8
Features (28-Pin Devices) ........................................... 9
New Core Features ...................................................... 7
Other Special Features ................................................ 8
Oscillator Start-up Timer (OST) ............................... 245
PLL Lock Time-out ................................................... 245
Power-up Timer (PWRT) ......................................... 245
Time-out Sequence .................................................. 245
Associated Registers ............................................... 130
Enhanced PWM Mode ............................................. 115
Outputs and Configuration ....................................... 112
Specifications ........................................................... 347
Receiver Transmitter (EUSART) .............................. 173
Asynchronous Mode ................................................ 175
Baud Rate Generator (BRG)
Clock polarity
Auto-Restart ..................................................... 124
Auto-shutdown ................................................. 123
Direction Change in Full-Bridge Output Mode . 121
Full-Bridge Application ..................................... 119
Full-Bridge Mode ............................................. 119
Half-Bridge Application .................................... 118
Half-Bridge Application Examples ................... 125
Half-Bridge Mode ............................................. 118
Output Relationships (Active-High and
Output Relationships Diagram ......................... 117
Programmable Dead Band Delay .................... 125
Shoot-through Current ..................................... 125
Start-up Considerations ................................... 122
12-bit Break Transmit and Receive ................. 192
Associated Registers, Receive ........................ 181
Associated Registers, Transmit ....................... 177
Auto-Wake-up on Break .................................. 190
Baud Rate Generator (BRG) ........................... 185
Clock Accuracy ................................................ 182
Receiver ........................................................... 178
Setting up 9-bit Mode with Address Detect ...... 180
Transmitter ....................................................... 175
Associated Registers ....................................... 185
Auto Baud Rate Detect .................................... 189
Baud Rate Error, Calculating ........................... 185
Baud Rates, Asynchronous Modes ................. 186
Formulas .......................................................... 185
High Baud Rate Select (BRGH Bit) ................. 185
Synchronous Mode .......................................... 193
Active-Low) .............................................. 116
Preliminary
PIC18F1XK22/LF1XK22
Extended Instruction Set
F
Fail-Safe Clock Monitor ............................................. 23, 253
Fast Register Stack ........................................................... 28
Firmware Instructions ...................................................... 269
Flash Program Memory ..................................................... 47
G
General Call Address Support ......................................... 156
GOTO .............................................................................. 290
H
Hardware Multiplier ............................................................ 61
Data polarity
Interrupts
Synchronous Master Mode .............................. 193, 198
Synchronous Slave Mode
ADDFSR .................................................................. 312
ADDULNK ............................................................... 312
and Using MPLAB Tools ......................................... 318
CALLW .................................................................... 313
Considerations for Use ............................................ 316
MOVSF .................................................................... 313
MOVSS .................................................................... 314
PUSHL ..................................................................... 314
SUBFSR .................................................................. 315
SUBULNK ................................................................ 315
Syntax ...................................................................... 311
Fail-Safe Condition Clearing ...................................... 23
Fail-Safe Detection .................................................... 23
Fail-Safe Operation ................................................... 23
Reset or Wake-up from Sleep ................................... 23
Associated Registers ................................................. 55
Control Registers ....................................................... 48
Erase Sequence ........................................................ 52
Erasing ...................................................................... 52
Operation During Code-Protect ................................. 55
Reading ..................................................................... 51
Table Pointer
Table Pointer Boundaries .......................................... 50
Table Reads and Table Writes .................................. 47
Write Sequence ......................................................... 53
Writing To .................................................................. 53
Introduction ................................................................ 61
Operation ................................................................... 61
Performance Comparison .......................................... 61
Asynchronous Receive .................................... 178
Asynchronous Transmit ................................... 175
Synchronous Mode .......................................... 193
Asynchronous Receive .................................... 179
Asynchronous Transmit ................................... 175
Associated Registers, Receive ........................ 197
Associated Registers, Transmit ............... 195, 198
Reception ........................................................ 196
Transmission ................................................... 193
Associated Registers, Receive ........................ 199
Reception ........................................................ 199
Transmission ................................................... 198
EECON1 and EECON2 ..................................... 48
TABLAT (Table Latch) Register ........................ 50
TBLPTR (Table Pointer) Register ...................... 50
Boundaries Based on Operation ....................... 50
Protection Against Spurious Writes ................... 55
Unexpected Termination ................................... 55
Write Verify ........................................................ 55
DS41365B-page 369