PIC18F13K22-I/ML Microchip Technology, PIC18F13K22-I/ML Datasheet - Page 376

• Manufacturer Part Number: PIC18F13K22-I/ML
• Description: IC MCU 8BIT 8KB FLASH 20-QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F13K22-I/ML

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, MSSP, SPI, USART
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F1XK22/LF1XK22
Timer2 .............................................................................. 105
Timer3 .............................................................................. 107
Timing Diagrams
DS41365B-page 374
Oscillator ............................................................ 99, 102
Overflow Interrupt ...................................................... 99
Resetting, Using the CCP Special Event Trigger ..... 103
Specifications ........................................................... 346
TMR1H Register ........................................................ 99
TMR1L Register ......................................................... 99
Use as a Real-Time Clock ....................................... 103
Associated Registers ............................................... 106
Interrupt .................................................................... 106
Operation ................................................................. 105
Output ...................................................................... 106
16-Bit Read/Write Mode ........................................... 110
Associated Registers ............................................... 110
Operation ................................................................. 108
Oscillator .......................................................... 107, 110
Overflow Interrupt ............................................ 107, 110
Special Event Trigger (CCP) .................................... 110
TMR3H Register ...................................................... 107
TMR3L Register ....................................................... 107
A/D Conversion ........................................................ 348
Acknowledge Sequence .......................................... 166
Asynchronous Reception ......................................... 180
Asynchronous Transmission .................................... 176
Asynchronous Transmission (Back to Back) ........... 177
Auto Wake-up Bit (WUE) During Normal Operation 191
Auto Wake-up Bit (WUE) During Sleep ................... 191
Automatic Baud Rate Calculator .............................. 189
Baud Rate Generator with Clock Arbitration ............ 160
BRG Reset Due to SDA Arbitration During Start
Brown-out Reset (BOR) ........................................... 344
Bus Collision During a Repeated Start Condition
Bus Collision During a Repeated Start Condition (
Bus Collision During a Start Condition (SCL = 0) .... 169
Bus Collision During a Stop Condition (Case 1) ...... 171
Bus Collision During a Stop Condition (Case 2) ...... 171
Bus Collision During Start Condition (SDA only) ..... 168
Bus Collision for Transmit and Acknowledge ........... 167
CLKOUT and I/O ...................................................... 343
Clock Synchronization ............................................. 153
Clock Timing ............................................................ 341
Clock/Instruction Cycle .............................................. 29
Comparator Output .................................................. 215
Enhanced Capture/Compare/PWM (ECCP) ............ 347
Fail-Safe Clock Monitor (FSCM) ................................ 24
First Start Bit Timing ................................................ 161
Full-Bridge PWM Output .......................................... 120
Half-Bridge PWM Output ................................. 118, 125
I
I
I
I
I
I
I
I
I
I
I
2
2
2
2
2
2
2
2
2
2
2
C Bus Data ............................................................ 354
C Bus Start/Stop Bits ............................................. 353
C Master Mode (7 or 10-Bit Transmission) ........... 164
C Master Mode (7-Bit Reception) .......................... 165
C Slave Mode (10-Bit Reception, SEN = 0) .......... 148
C Slave Mode (10-Bit Reception, SEN = 1) .......... 155
C Slave Mode (10-Bit Transmission) ..................... 149
C Slave Mode (7-bit Reception, SEN = 0) ............. 146
C Slave Mode (7-Bit Reception, SEN = 1) ............ 154
C Slave Mode (7-Bit Transmission) ....................... 147
C Slave Mode General Call Address Sequence
Condition .......................................................... 169
(Case 1) ........................................................... 170
Case 2) ............................................................ 170
(7 or 10-Bit Address Mode) .............................. 156
Preliminary
Timing Diagrams and Specifications
Timing Parameter Symbology ......................................... 340
Timing Requirements
Top-of-Stack Access .......................................................... 26
TRISA Register .................................................................. 79
TRISB Register ............................................................ 84, 88
TSTFSZ ........................................................................... 309
Two-Speed Start-up ......................................................... 253
Two-Word Instructions
TXREG ............................................................................ 175
TXSTA Register ............................................................... 182
U
USART
I
Internal Oscillator Switch Timing ............................... 21
PWM Auto-shutdown
PWM Direction Change ........................................... 121
PWM Direction Change at Near 100% Duty Cycle .. 122
PWM Output (Active-High) ...................................... 116
PWM Output (Active-Low) ....................................... 117
Repeat Start Condition ............................................ 162
Reset, WDT, OST and Power-up Timer .................. 344
Send Break Character Sequence ............................ 192
Slave Synchronization ............................................. 137
Slow Rise Time (MCLR Tied to V
SPI Master Mode (CKE = 1, SMP = 1) .................... 351
SPI Mode (Master Mode) ......................................... 136
SPI Mode (Slave Mode, CKE = 0) ........................... 138
SPI Mode (Slave Mode, CKE = 1) ........................... 138
SPI Slave Mode (CKE = 0) ...................................... 352
SPI Slave Mode (CKE = 1) ...................................... 352
Synchronous Reception (Master Mode, SREN) ...... 197
Synchronous Transmission ..................................... 194
Synchronous Transmission (Through TXEN) .......... 194
Time-out Sequence on POR w/PLL Enabled
Time-out Sequence on Power-up (MCLR Not
Time-out Sequence on Power-up (MCLR Not
Time-out Sequence on Power-up (MCLR
Timer0 and Timer1 External Clock .......................... 346
Transition for Entry to Sleep Mode .......................... 229
Transition for Wake from Sleep (HSPLL) ................ 229
Transition Timing for Entry to Idle Mode .................. 230
Transition Timing for Wake from Idle to Run Mode . 230
USART Synchronous Receive (Master/Slave) ........ 350
USART Synchronous Transmission
A/D Conversion Requirements ................................ 348
PLL Clock ................................................................ 342
I
I2C Bus Start/Stop Bits ............................................ 354
SPI Mode ................................................................. 353
Example Cases .......................................................... 30
BRGH Bit ................................................................. 185
Synchronous Master Mode
2
2
C Stop Condition Receive or Transmit Mode ........ 166
C Bus Data ............................................................ 355
Auto-restart Enabled ........................................ 124
Firmware Restart ............................................. 124
T
(MCLR Tied to V
Tied to V
Tied to V
Tied to V
(Master/Slave) ................................................. 350
Requirements, Synchronous Receive ............. 350
Requirements, Synchronous Transmission ..... 350
Timing Diagram, Synchronous Receive .......... 350
Timing Diagram, Synchronous Transmission .. 350
PWRT
) ............................................................. 247
DD
DD
DD
, Case 1) ....................................... 246
, Case 2) ....................................... 246
, V
DD
© 2009 Microchip Technology Inc.
DD
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) ........................................ 247
PWRT
DD
, V
) ..................... 246
DD
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