PIC18F13K22-I/ML Microchip Technology, PIC18F13K22-I/ML Datasheet - Page 370

• Manufacturer Part Number: PIC18F13K22-I/ML
• Description: IC MCU 8BIT 8KB FLASH 20-QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F13K22-I/ML

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, MSSP, SPI, USART
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F1XK22/LF1XK22
CALL ................................................................................ 284
CALLW ............................................................................. 313
Capture (CCP Module) ..................................................... 113
Capture/Compare/PWM (CCP)
CCP1CON Register ......................................................... 111
Clock Accuracy with Asynchronous Operation ................ 182
Clock Sources
CLRF ................................................................................ 285
CLRWDT .......................................................................... 285
CM1CON0 Register ......................................................... 221
CM2CON0 Register ......................................................... 222
CM2CON1 Register ......................................................... 225
Code Examples
Code Protection ............................................................... 253
COMF ............................................................................... 286
Comparator
Comparator Module ......................................................... 215
Comparator Specifications ............................................... 349
Comparator Voltage Reference (CV
Comparator Voltage Reference (CV
Comparators
DS41365B-page 368
CCP Pin Configuration ............................................. 113
CCPRxH:CCPRxL Registers ................................... 113
Prescaler .................................................................. 113
Software Interrupt .................................................... 113
Timer1/Timer3 Mode Selection ................................ 113
Capture Mode. See Capture.
CCP Mode and Timer Resources ............................ 112
Compare Mode. See Compare.
Associated registers ................................................... 24
External Modes
16 x 16 Signed Multiply Routine ................................ 62
16 x 16 Unsigned Multiply Routine ............................ 62
8 x 8 Signed Multiply Routine .................................... 61
8 x 8 Unsigned Multiply Routine ................................ 61
A/D Conversion ........................................................ 206
Changing Between Capture Prescalers ................... 113
Clearing RAM Using Indirect Addressing ................... 41
Computed GOTO Using an Offset Value ................... 28
Data EEPROM Read ................................................. 59
Data EEPROM Refresh Routine ................................ 60
Data EEPROM Write ................................................. 59
Erasing a Flash Program Memory Row ..................... 52
Fast Register Stack .................................................... 28
Implementing a Timer1 Real-Time Clock ................. 104
Initializing PORTA ...................................................... 78
Initializing PORTB ...................................................... 83
Initializing PORTC ...................................................... 88
Loading the SSPBUF (SSPSR) Register ................. 134
Reading a Flash Program Memory Word .................. 51
Saving Status, WREG and BSR Registers in RAM ... 75
Writing to Flash Program Memory ....................... 54–55
Associated Registers ............................................... 226
Operation ................................................................. 215
Operation During Sleep ........................................... 220
Response Time ........................................................ 218
C1 Output State Versus Input Conditions ................ 218
Associated Registers ............................................... 240
Effects of a Reset ............................................. 220, 237
Operation During Sleep ........................................... 237
Overview .................................................................. 237
Response Time ........................................................ 218
HS ...................................................................... 15
LP ....................................................................... 15
XT ...................................................................... 15
REF
REF
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)
Preliminary
Compare (CCP Module) .................................................. 114
Computed GOTO ............................................................... 28
CONFIG1H Register ........................................................ 255
CONFIG2H Register ........................................................ 257
CONFIG2L Register ........................................................ 256
CONFIG3H Register ........................................................ 258
CONFIG4L Register ........................................................ 258
CONFIG5H Register ........................................................ 259
CONFIG5L Register ........................................................ 259
CONFIG6H Register ........................................................ 260
CONFIG6L Register ........................................................ 260
CONFIG7H Register ........................................................ 261
CONFIG7L Register ........................................................ 261
Configuration Bits ............................................................ 254
Configuration Register Protection .................................... 268
Context Saving During Interrupts ....................................... 75
CPFSEQ .......................................................................... 286
CPFSGT .......................................................................... 287
CPFSLT ........................................................................... 287
Customer Change Notification Service ............................ 377
Customer Notification Service ......................................... 377
Customer Support ............................................................ 377
CV
D
Data Addressing Modes .................................................... 41
Data EEPROM
Data EEPROM Memory ..................................................... 57
Data Memory ..................................................................... 31
DAW ................................................................................ 288
DC and AC Characteristics
DC Characteristics
REF
Effects of a Reset .................................................... 220
CCPRx Register ...................................................... 114
Pin Configuration ..................................................... 114
Software Interrupt .................................................... 114
Special Event Trigger ...................................... 110, 114
Timer1/Timer3 Mode Selection ................................ 114
Comparing Addressing Modes with the
Direct ......................................................................... 41
Indexed Literal Offset ................................................ 43
Indirect ....................................................................... 41
Inherent and Literal .................................................... 41
Code Protection ....................................................... 268
Associated Registers ................................................. 60
EEADR and EEADRH Registers ............................... 57
EECON1 and EECON2 Registers ............................. 57
Operation During Code-Protect ................................. 60
Protection Against Spurious Write ............................. 60
Reading ..................................................................... 59
Using ......................................................................... 60
Write Verify ................................................................ 59
Writing ....................................................................... 59
Access Bank .............................................................. 35
Access RAM .............................................................. 31
and the Extended Instruction Set .............................. 43
Bank Select Register (BSR) ...................................... 31
General Purpose Registers ....................................... 35
Map for PIC18F13K50/PIC18LF13K50 ..................... 32
Map for PIC18F14K50/PIC18LF14K50 ..................... 33
Special Function Registers ........................................ 35
Graphs and Tables .................................................. 357
Extended and Industrial ........................................... 336
Industrial and Extended ........................................... 326
Voltage Reference Specifications ........................ 349
Extended Instruction Set Enabled ..................... 44
Instructions Affected .......................................... 43
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