PIC18F1320-I/SS Microchip Technology, PIC18F1320-I/SS Datasheet - Page 118

• Manufacturer Part Number: PIC18F1320-I/SS
• Description: IC MCU FLASH 4KX16 A/D 20SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F1320-I/SS

• Core Size: 8-Bit
• Program Memory Size: 8KB (4K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SSOP
• Controller Family/series: PIC18
• No. Of I/o's: 16
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 256Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 7 bit
• Package: 20SSOP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPAC164307 - MODULE SKT FOR PM3 28SSOPAC164018 - MODULE SKT PROMATEII 20SSOP
• Lead Free Status / Rohs Status: Details

PIC18F1220/1320
15.1
The Enhanced CCP module may have up to four
outputs, depending on the selected operating mode.
These outputs, designated P1A through P1D, are
multiplexed with I/O pins on PORTB. The pin
assignments are summarized in Table 15-1.
TABLE 15-1:
15.2
Capture/Compare/PWM Register 1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. All are readable and writable.
TABLE 15-2:
15.3
In Capture mode, CCPR1H:CCPR1L captures the 16-bit
value of the TMR1 or TMR3 registers when an event
occurs on pin RB3/CCP1/P1A. An event is defined as
one of the following:
• every falling edge
• every rising edge
• every 4th rising edge
• every 16th rising edge
The event is selected by control bits, CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request flag bit, CCP1IF (PIR1<2>), is set; it must
be cleared in software. If another capture occurs before
the value in register CCPR1 is read, the old captured
value is overwritten by the new captured value.
DS39605F-page 116
Compatible CCP
Dual PWM
Quad PWM
Legend:
Note 1:
ECCP Mode
CCP Mode
Compare
Capture
ECCP Outputs
CCP Module
Capture Mode
PWM
x = Don’t care. Shaded cells indicate pin assignments not used by ECCP in a given mode.
TRIS register values must be configured appropriately.
PIN ASSIGNMENTS FOR VARIOUS ECCP MODES
CCP MODE – TIMER
RESOURCE
Configuration
00xx 11xx
10xx 11xx
x1xx 11xx
CCP1CON
Timer1 or Timer3
Timer1 or Timer3
Timer Resource
Timer2
CCP1
RB3
P1A
P1A
RB2/INT2
RB2
P1B
P1B
RB6/PGC/T1OSO/T13CKI/KBI2
RB6/PGC/T1OSO/T13CKI/KBI2
To configure I/O pins as PWM outputs, the proper PWM
mode must be selected by setting the P1Mn and
CCP1Mn
respectively). The appropriate TRISB direction bits for
the port pins must also be set as outputs.
15.3.1
In Capture mode, the RB3/CCP1/P1A pin should be
configured as an input by setting the TRISB<3> bit.
15.3.2
The timers that are to be used with the capture feature
(either Timer1 and/or Timer3) must be running in Timer
mode or Synchronized Counter mode. In Asynchro-
nous Counter mode, the capture operation may not
work. The timer to be used with the CCP module is
selected in the T3CON register.
15.3.3
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit,
CCP1IE (PIE1<2>), clear while changing capture
modes to avoid false interrupts and should clear the
flag bit, CCP1IF, following any such change in
operating mode.
Note:
RB6
P1C
CCP PIN CONFIGURATION
If the RB3/CCP1/P1A is configured as an
output, a write to the port can cause a
capture condition.
TIMER1/TIMER3 MODE SELECTION
SOFTWARE INTERRUPT
bits
(CCP1CON<7:6>
© 2007 Microchip Technology Inc.
RB7/PGD/T1OSI/KBI3
RB7/PGD/T1OSI/KBI3
RB7
P1D
and
<3:0>,