PIC18F1320-I/SS Microchip Technology, PIC18F1320-I/SS Datasheet - Page 166

• Manufacturer Part Number: PIC18F1320-I/SS
• Description: IC MCU FLASH 4KX16 A/D 20SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F1320-I/SS

• Core Size: 8-Bit
• Program Memory Size: 8KB (4K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SSOP
• Controller Family/series: PIC18
• No. Of I/o's: 16
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 256Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 7 bit
• Package: 20SSOP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPAC164307 - MODULE SKT FOR PM3 28SSOPAC164018 - MODULE SKT PROMATEII 20SSOP
• Lead Free Status / Rohs Status: Details

PIC18F1220/1320
17.8
An A/D conversion can be started by the “special event
trigger” of the CCP1 module. This requires that the
CCP1M3:CCP1M0 bits (CCP1CON<3:0>) be pro-
grammed as ‘1011’ and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D acquisition
and conversion and the Timer1 (or Timer3) counter will
be reset to zero. Timer1 (or Timer3) is reset to auto-
matically repeat the A/D acquisition period with minimal
TABLE 17-2:
DS39605F-page 164
INTCON
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
PORTA
TRISA
PORTB
TRISB
LATB
Legend:
Note 1:
Name
2:
3:
Use of the CCP1 Trigger
Read PORTB pins, Write LATB Latch
PORTB Data Direction Register
PORTB Output Data Latch
TRISA7
A/D Result Register High Byte
A/D Result Register Low Byte
x = unknown, u = unchanged, q = depends on CONFIG1H<3:0>, – = unimplemented, read as ‘0’.
Shaded cells are not used for A/D conversion.
RA5 port bit is available only as an input pin when the MCLRE bit in the configuration register is ‘0’.
RA6 and TRISA6 are available only when the primary oscillator mode selection offers RA6 as a port pin; otherwise, RA6
always reads ‘0’, TRISA6 always reads ‘1’ and writes to both are ignored (see CONFIG1H<3:0>).
RA7 and TRISA7 are available only when the internal RC oscillator is configured as the primary oscillator in
CONFIG1H<3:0>; otherwise, RA7 always reads ‘0’, TRISA7 always reads ‘1’ and writes to both are ignored.
OSCFIE
OSCFIP
OSCFIF
VCFG1
ADFM
RA7
GIEH
Bit 7
GIE/
—
—
—
—
(3)
SUMMARY OF A/D REGISTERS
(3)
TRISA6
VCFG0
PCFG6
RA6
PEIE/
ADIE
ADIP
GIEL
ADIF
Bit 6
—
—
—
—
(2)
(2)
TMR0IE
PCFG5
ACQT2
RA5
RCIF
RCIE
RCIP
Bit 5
—
—
—
—
—
(1)
PORTA Data Direction Register
PCFG4
ACQT1
INT0IE
CHS2
TXIF
TXIE
TXIP
EEIF
EEIE
EEIP
Bit 4
RA4
PCFG3
ACQT0
CHS1
RBIE
Bit 3
RA3
—
—
—
—
—
—
TMR0IF
CCP1IE
CCP1IP
CCP1IF
PCFG2
ADCS2
LVDIE
LVDIP
LVDIF
CHS0
software overhead (moving ADRESH/ADRESL to the
desired location). The appropriate analog input
channel must be selected and the minimum acquisition
period is either timed by the user, or an appropriate
T
sets the GO/DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared), the
“special event trigger” will be ignored by the A/D
module, but will still reset the Timer1 (or Timer3)
counter.
Bit 2
RA2
ACQ
time selected before the “special event trigger”
GO/DONE
TMR2IF
TMR2IE
TMR2IP
TMR3IF
TMR3IE
TMR3IP
PCFG1
ADCS1
INT0IF
Bit 1
RA1
TMR1IF
TMR1IE
TMR1IP
PCFG0
ADCS0
ADON
RBIF
Bit 0
RA0
—
—
—
© 2007 Microchip Technology Inc.
0000 0000
-000 -000
-000 -000
-111 -111
0--0 -00-
0--0 -00-
1--1 -11-
xxxx xxxx
xxxx xxxx
00-0 0000
-000 0000
0-00 0000
qq0x 0000
qq-1 1111
xxxx xxxx
1111 1111
xxxx xxxx
POR, BOR
Value on
0000 0000
-000 -000
-000 -000
-111 -111
0--0 -00-
0--0 -00-
1--1 -11-
uuuu uuuu
uuuu uuuu
00-0 0000
-000 0000
0-00 0000
uu0u 0000
11-1 1111
uuuu uuuu
1111 1111
uuuu uuuu
Value on
all other
Resets