PIC18F1320-I/SS Microchip Technology, PIC18F1320-I/SS Datasheet - Page 302

• Manufacturer Part Number: PIC18F1320-I/SS
• Description: IC MCU FLASH 4KX16 A/D 20SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F1320-I/SS

• Core Size: 8-Bit
• Program Memory Size: 8KB (4K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SSOP
• Controller Family/series: PIC18
• No. Of I/o's: 16
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 256Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 7 bit
• Package: 20SSOP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPAC164307 - MODULE SKT FOR PM3 28SSOPAC164018 - MODULE SKT PROMATEII 20SSOP
• Lead Free Status / Rohs Status: Details

PIC18F1220/1320
RESET ............................................................................. 221
Reset .......................................................................... 33, 171
RETFIE ............................................................................ 222
RETLW ............................................................................. 222
RETURN .......................................................................... 223
Return Address Stack ........................................................ 42
Return Stack Pointer (STKPTR) ........................................ 42
Revision History ............................................................... 291
RLCF ................................................................................ 223
RLNCF ............................................................................. 224
RRCF ............................................................................... 224
RRNCF ............................................................................. 225
S
SETF ................................................................................ 225
SLEEP .............................................................................. 226
Sleep
Software Simulator (MPLAB SIM) .................................... 234
Special Event Trigger. See Compare
Special Features of the CPU ............................................ 171
Special Function Registers ................................................ 49
Stack Full/Underflow Resets .............................................. 43
SUBFWB .......................................................................... 226
SUBLW ............................................................................ 227
SUBWF ............................................................................ 227
SUBWFB .......................................................................... 228
SWAPF ............................................................................ 228
T
TABLAT Register ............................................................... 60
Table Pointer Operations (table) ........................................ 60
TBLPTR Register ............................................................... 60
TBLRD ............................................................................. 229
TBLWT ............................................................................. 230
Time-out Sequence ............................................................ 34
Timer0 ................................................................................ 99
DS39605F-page 300
OSCTUNE (Oscillator Tuning) ................................... 15
PIE1 (Peripheral Interrupt Enable 1) .......................... 80
PIE2 (Peripheral Interrupt Enable 2) .......................... 81
PIR1 (Peripheral Interrupt Request (Flag) 1) ............. 78
PIR2 (Peripheral Interrupt Request (Flag) 2) ............. 79
PWM1CON (PWM Configuration) ............................ 126
RCON (Reset Control) ......................................... 56, 84
RCSTA (Receive Status and Control) ...................... 133
Status ......................................................................... 55
STKPTR (Stack Pointer) ............................................ 43
T0CON (Timer0 Control) ............................................ 99
T1CON (Timer 1 Control) ......................................... 103
T2CON (Timer 2 Control) ......................................... 109
T3CON (Timer3 Control) .......................................... 111
TXSTA (Transmit Status and Control) ..................... 132
WDTCON (Watchdog Timer Control) ....................... 180
and Associated Registers .......................................... 42
OSC1 and OSC2 Pin States ...................................... 18
Configuration Registers .................................... 172–178
Map ............................................................................ 49
16-Bit Mode Timer Reads and Writes ...................... 101
Associated Registers ............................................... 101
Clock Source Edge Select (T0SE Bit) ...................... 101
Clock Source Select (T0CS Bit) ............................... 101
Operation ................................................................. 101
Overflow Interrupt ..................................................... 101
Prescaler. See Prescaler, Timer0.
Switching Prescaler Assignment .............................. 101
Timer1 .............................................................................. 103
Timer2 .............................................................................. 109
Timer3 .............................................................................. 111
Timing Diagrams
16-Bit Read/Write Mode .......................................... 106
Associated Registers ............................................... 108
Interrupt ................................................................... 106
Operation ................................................................. 104
Oscillator ...........................................................103, 105
Overflow Interrupt .................................................... 103
Resetting, Using a Special Event Trigger
Special Event Trigger (CCP) ................................... 117
TMR1H Register ...................................................... 103
TMR1L Register ....................................................... 103
Use as a Real-Time Clock ....................................... 107
Associated Registers ............................................... 110
Operation ................................................................. 109
Output ...................................................................... 110
Postscaler. See Postscaler, Timer2.
PR2 Register ....................................................109, 119
Prescaler. See Prescaler, Timer2.
TMR2 Register ......................................................... 109
TMR2 to PR2 Match Interrupt ...................109, 110, 119
Associated Registers ............................................... 113
Operation ................................................................. 112
Oscillator ...........................................................111, 113
Overflow Interrupt .............................................111, 113
Special Event Trigger (CCP) ................................... 113
TMR3H Register ...................................................... 111
TMR3L Register ....................................................... 111
A/D Conversion ........................................................ 265
Asynchronous Reception ......................................... 144
Asynchronous Transmission .................................... 141
Asynchronous Transmission (Back to Back) ........... 142
Auto-Wake-up Bit (WUE) During
Auto-Wake-up Bit (WUE) During Sleep ................... 145
Brown-out Reset (BOR) ........................................... 260
Capture/Compare/PWM (All CCP Modules) ............ 262
CLKO and I/O .......................................................... 259
Clock/Instruction Cycle .............................................. 45
EUSART Synchronous Receive
EUSART SynchronousTransmission
External Clock (All Modes Except PLL) ................... 257
Fail-Safe Clock Monitor ........................................... 183
Low-Voltage Detect ................................................. 168
Low-Voltage Detect Characteristics ......................... 253
PWM Auto-Shutdown (PRSEN = 0,
PWM Auto-Shutdown (PRSEN = 1,
Reset, Watchdog Timer (WDT), Oscillator Start-up
Send Break Character Sequence ............................ 147
Slow Rise Time (MCLR Tied to V
Synchronous Reception
Synchronous Transmission ..................................... 148
Synchronous Transmission (Through TXEN) .......... 149
Layout Considerations ..................................... 106
Output (CCP) ................................................... 106
Normal Operation ............................................ 145
(Master/Slave) ................................................. 264
(Master/Slave) ................................................. 263
Auto-Restart Disabled) .................................... 128
Auto-Restart Enabled) ..................................... 128
Timer (OST) and Power-up Timer (PWRT) ..... 260
V
(Master Mode, SREN) ..................................... 150
DD
Rise > T
PWRT
© 2007 Microchip Technology Inc.
) ............................................ 40
DD
,