PIC18F1320-I/SS Microchip Technology, PIC18F1320-I/SS Datasheet - Page 183

• Manufacturer Part Number: PIC18F1320-I/SS
• Description: IC MCU FLASH 4KX16 A/D 20SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F1320-I/SS

• Core Size: 8-Bit
• Program Memory Size: 8KB (4K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SSOP
• Controller Family/series: PIC18
• No. Of I/o's: 16
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 256Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 7 bit
• Package: 20SSOP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPAC164307 - MODULE SKT FOR PM3 28SSOPAC164018 - MODULE SKT PROMATEII 20SSOP
• Lead Free Status / Rohs Status: Details

TABLE 19-2:
19.3
The Two-Speed Start-up feature helps to minimize the
latency period from oscillator start-up to code execution
by allowing the microcontroller to use the INTRC oscil-
lator as a clock source until the primary clock source is
available. It is enabled by setting the IESO bit in
Configuration Register 1H (CONFIG1H<7>).
Two-Speed Start-up is available only if the primary oscil-
lator mode is LP, XT, HS or HSPLL (crystal-based
modes). Other sources do not require an OST start-up
delay; for these, Two-Speed Start-up is disabled.
When enabled, Resets and wake-ups from Sleep mode
cause the device to configure itself to run from the
internal oscillator block as the clock source, following
the time-out of the Power-up Timer after a Power-on
Reset is enabled. This allows almost immediate code
execution while the primary oscillator starts and the
OST is running. Once the OST times out, the device
automatically switches to PRI_RUN mode.
Because the OSCCON register is cleared on Reset
events, the INTOSC (or postscaler) clock source is not
initially available after a Reset event; the INTRC clock
is used directly at its base frequency. To use a higher
clock speed on wake-up, the INTOSC or postscaler
clock sources can be selected to provide a higher clock
speed by setting bits, IFRC2:IFRC0, immediately after
Reset. For wake-ups from Sleep, the INTOSC or
postscaler clock sources can be selected by setting
IFRC2:IFRC0 prior to entering Sleep mode.
FIGURE 19-2:
© 2007 Microchip Technology Inc.
CONFIG2H
RCON
WDTCON
Legend:
Name
Note
CPU Clock
Multiplexer
PLL Clock
Peripheral
Program
INTOSC
Counter
Two-Speed Start-up
Output
OSC1
Clock
Shaded cells are not used by the Watchdog Timer.
1: T
Wake from Interrupt Event
OST
SUMMARY OF WATCHDOG TIMER REGISTERS
IPEN
Bit 7
= 1024 T
—
—
PC
TIMING TRANSITION FOR TWO-SPEED START-UP (INTOSC TO HSPLL)
OSC
; T
Q1
PLL
T
Bit 6
OST (1)
—
—
—
= 2 ms (approx). These intervals are not shown to scale.
Q2
PC + 2
OSTS bit Set
T
Q3
PLL
Bit 5
—
—
—
(1)
Q4
WDTPS3
Bit 4
Q1
1
RI
—
2
In all other power managed modes, Two-Speed Start-up
is not used. The device will be clocked by the currently
selected clock source until the primary clock source
becomes available. The setting of the IESO bit is
ignored.
19.3.1
While using the INTRC oscillator in Two-Speed Start-
up, the device still obeys the normal command
sequences for entering power managed modes, includ-
ing serial SLEEP instructions (refer to Section 3.1.3
“Multiple Sleep Commands”). In practice, this means
that user code can change the SCS1:SCS0 bit settings
and issue SLEEP commands before the OST times out.
This would allow an application to briefly wake-up, per-
form routine “housekeeping” tasks and return to Sleep
before the device starts to operate from the primary
oscillator.
User code can also check if the primary clock source is
currently providing the system clocking by checking the
status of the OSTS bit (OSCCON<3>). If the bit is set,
the primary oscillator is providing the system clock.
Otherwise, the internal oscillator block is providing the
clock during wake-up from Reset or Sleep mode.
Clock Transition
3
WDTPS2
4
Bit 3
TO
—
PIC18F1220/1320
5
PC + 4
SPECIAL CONSIDERATIONS FOR
USING TWO-SPEED START-UP
6
7
WDTPS2
8
Bit 2
PD
—
Q2
Q3 Q4
WDTPS0
POR
Bit 1
—
Q1
DS39605F-page 181
Q2
PC + 6
Q3 Q4
SWDTEN
WDTEN
Bit 0
BOR