PIC18F6310-I/PT Microchip Technology, PIC18F6310-I/PT Datasheet - Page 146

• Manufacturer Part Number: PIC18F6310-I/PT
• Description: IC PIC MCU FLASH 4KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6310-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SPI/I2C/EUSART/AUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 4
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F6310/6410/8310/8410
11.1
Timer0 can operate as either a timer or a counter; the
mode is selected by clearing the T0CS bit (T0CON<5>).
In Timer mode (T0CS = 0), the module increments on
every clock by default, unless a different prescaler value
is selected (see Section 11.3 “Prescaler”). If the TMR0
register is written to, the increment is inhibited for the fol-
lowing two instruction cycles. The user can work around
this by writing an adjusted value to the TMR0 register.
The Counter mode is selected by setting the T0CS bit
(= 1). In Counter mode, Timer0 increments either on
every rising or falling edge of pin RA4/T0CKI. The
incrementing edge is determined by the Timer0 Source
Edge Select bit, T0SE (T0CON<4>); clearing this bit
selects the rising edge. Restrictions on the external
clock input are discussed below.
An external clock source can be used to drive Timer0;
however, it must meet certain requirements to ensure
that the external clock can be synchronized with the
FIGURE 11-1:
FIGURE 11-2:
DS39635A-page 144
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI maximum prescale.
T0CKI pin
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI maximum prescale.
T0CKI pin
Timer0 Operation
T0SE
T0CS
T0PS2:T0PS0
PSA
F
OSC
T0SE
T0CS
T0PS2:T0PS0
PSA
F
/4
OSC
/4
TIMER0 BLOCK DIAGRAM (8-BIT MODE)
TIMER0 BLOCK DIAGRAM (16-BIT MODE)
0
1
0
1
Programmable
Prescaler
Programmable
Prescaler
3
3
0
1
Preliminary
0
1
(2 T
Sync with
Internal
Clocks
CY
(2 T
Sync with
Delay)
Internal
Clocks
CY
internal phase clock (T
synchronization and the onset of incrementing the
timer/counter.
11.2
TMR0H is not the actual high byte of Timer0 in 16-bit
mode; it is actually a buffered version of the real high
byte of Timer0, which is not directly readable nor
writable (refer to Figure 11-2). TMR0H is updated with
the contents of the high byte of Timer0 during a read of
TMR0L. This provides the ability to read all 16 bits of
Timer0, without having to verify that the read of the high
and low byte were valid, due to a rollover between
successive reads of the high and low byte.
Similarly, a write to the high byte of Timer0 must also
take place through the TMR0H Buffer register. The high
byte is updated with the contents of TMR0H when a
write occurs to TMR0L. This allows all 16 bits of Timer0
to be updated at once.
Delay)
Timer0 Reads and Writes in
16-Bit Mode
TMR0L
8
TMR0L
8
8
8
OSC
 2004 Microchip Technology Inc.
High Byte
TMR0H
TMR0
8
). There is a delay between
8
on Overflow
Internal Data Bus
TMR0IF
8
Set
Internal Data Bus
Read TMR0L
Write TMR0L
on Overflow
TMR0IF
Set