PIC18F6310-I/PT Microchip Technology, PIC18F6310-I/PT Datasheet - Page 99

• Manufacturer Part Number: PIC18F6310-I/PT
• Description: IC PIC MCU FLASH 4KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6310-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SPI/I2C/EUSART/AUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 4
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

7.3.1
The presentation of control signals on the external
memory bus is different for the various operating
modes. Typical signal timing diagrams are shown in
Figure 7-4 through Figure 7-6.
FIGURE 7-8:
FIGURE 7-9:
 2004 Microchip Technology Inc.
Instruction
AD<15:8>
Execution
A<19:16>
AD<7:0>
Memory
Instruction
AD<15:8>
A<19:16>
Execution
Cycle
AD<7:0>
Memory
ALE
Apparent Q
OE
CE
8-BIT MODE TIMING
Cycle
WRL
Actual Q
BA0
ALE
OE
CE
‘1’
‘0’
Q1
EXTERNAL MEMORY BUS TIMING FOR TBLRD (MICROPROCESSOR MODE)
EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED
MICROCONTROLLER MODE)
Opcode Fetch
from 000100h
INST(PC – 2)
Q1
Q1
Q2
TBLRD *
ABh
TBLRD Cycle 1
Opcode Fetch
from 007556h
Q2
Q2
MOVLW 55h
Q3
3Ah
00h
Q4
Q3
Q3
0Eh
Q1
Q4
Q4
55h
PIC18F6310/6410/8310/8410
TBLRD Cycle 1
Opcode Fetch
from 000102h
MOVLW 55h
Q2
Preliminary
Q1
Q1
Q3
33h
Q2
Q2
Q4
Q3
Q3
Q1
TBLRD Cycle 2
33h
TBLRD Cycle 2
from 199E67h
from 199E67h
Table Read
TBLRD 92h
Q2
Q4
Q4
of 92h
0Ch
CFh
Q3
CFh
0Ch
Q4
Q1
92h
92h
Q4
Q4
Q2
1 T
Q1
CY
Wait
Opcode Fetch
from 000104h
Q4
Q3
ADDLW 55h
Q2
MOVLW
Q4
Q4
DS39635A-page 97
Q3
‘1’
‘0’
Q4