PIC18F6310-I/PT Microchip Technology, PIC18F6310-I/PT Datasheet - Page 77

• Manufacturer Part Number: PIC18F6310-I/PT
• Description: IC PIC MCU FLASH 4KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6310-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SPI/I2C/EUSART/AUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 4
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 5-3:
 2004 Microchip Technology Inc.
SPBRG1
RCREG1
TXREG1
TXSTA1
RCSTA1
IPR3
PIR3
PIE3
IPR2
PIR2
PIE2
IPR1
PIR1
PIE1
MEMCON
OSCTUNE
TRISJ
TRISH
TRISG
TRISF
TRISE
TRISD
TRISC
TRISB
TRISA
LATJ
LATH
LATG
LATF
LATE
LATD
LATC
LATB
LATA
PORTJ
PORTH
PORTG
PORTF
PORTE
PORTD
PORTC
PORTB
PORTA
Legend:
Note
File Name
(2)
(2)
(2)
(2)
(2)
(2)
1:
2:
3:
4:
5:
6:
(2)
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded locations are unimplemented, read as ‘0’.
The SBOREN bit is only available when the BOREN1:BOREN0 configuration bits = 01; otherwise it is disabled and reads as ‘0’. See
Section 4.4 “Brown-out Reset (BOR)”.
These registers and/or bits are not implemented on 64-pin devices, read as ‘0’.
The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in
INTOSC Modes”.
The RG5 bit is only available when Master Clear is disabled (MCLRE configuration bit = 0); otherwise, RG5 reads as ‘0’. This bit is
read-only.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
STKFUL and STKUNF bits are cleared by user software or by a POR.
EUSART1 Baud Rate Generator
EUSART1 Receive Register
EUSART1 Transmit Register
Data Direction Control Register for PORTJ
Data Direction Control Register for PORTH
Data Direction Control Register for PORTF
Data Direction Control Register for PORTE
Data Direction Control Register for PORTD
Data Direction Control Register for PORTC
Data Direction Control Register for PORTB
Read PORTJ Data Latch, Write PORTJ Data Latch
Read PORTH Data Latch, Write PORTH Data Latch
Read PORTF Data Latch, Write PORTF Data Latch
Read PORTE Data Latch, Write PORTE Data Latch
Read PORTD Data Latch, Write PORTD Data Latch
Read PORTC Data Latch, Write PORTC Data Latch
Read PORTB Data Latch, Write PORTB Data Latch
Read PORTJ pins, Write PORTJ Data Latch
Read PORTH pins, Write PORTH Data Latch
Read PORTF pins, Write PORTF Data Latch
Read PORTE pins, Write PORTE Data Latch
Read PORTD pins, Write PORTD Data Latch
Read PORTC pins, Write PORTC Data Latch
Read PORTB pins, Write PORTB Data Latch
TRISA7
LATA7
OSCFIP
OSCFIF
OSCFIE
INTSRC
PSPIP
PSPIE
EBDIS
CSRC
PSPIF
RA7
SPEN
Bit 7
—
—
—
—
—
—
(5)
REGISTER FILE SUMMARY (PIC18F6310/6410/8310/8410) (CONTINUED)
(5)
(5)
TRISA6
PLLEN
LATA6
RA6
CMIP
CMIF
CMIE
ADIP
ADIF
ADIE
Bit 6
RX9
TX9
—
—
—
—
—
—
—
(5)
(5)
(3)
(5)
Data Direction Control Register for PORTA
Read PORTA Data Latch, Write PORTA Data Latch
Read PORTA pins, Write PORTA Data Latch
WAIT1
RG5
RC2IP
RC2IF
RC2IE
RC1IP
RC1IF
RC1IE
TXEN
SREN
Bit 5
—
—
—
—
—
—
(4)
Data Direction Control Register for PORTG
Read PORTG Data Latch, Write PORTG Data Latch
Read PORTG pins <4:0>, Write PORTG Data Latch <4:0>
PIC18F6310/6410/8310/8410
WAIT0
SYNC
CREN
TX2IP
TX2IF
TX2IE
TX1IP
TX1IF
TX1IE
TUN4
Bit 4
—
—
—
Preliminary
SENDB
ADDEN
SSPIP
SSPIE
BCLIP
BCLIF
BCLIE
SSPIF
TUN3
Bit 3
—
—
—
—
CCP1IP
CCP1IF
CCP1IE
HLVDIP
HLVDIF
HLVDIE
BRGH
FERR
TUN2
Bit 2
—
—
—
—
TMR3IP
TMR3IF
TMR3IE
TMR2IP
TMR2IF
TMR2IE
OERR
TRMT
TUN1
WM1
Bit 1
—
—
—
TMR1IP
TMR1IE
CCP3IP
CCP3IF
CCP3IE
CCP2IP
CCP2IF
CCP2IE
TMR1IF
RX9D
TUN0
TX9D
WM0
Bit 0
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 0000
--00 ---1
--00 ---1
--00 ---1
11-- 1111
00-- 0000
00-- 0000
1111 1111
0000 0000
0000 0000
0-00 --00
00-0 0000
1111 1111
1111 1111
---1 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
xxxx xxxx
xxxx xxxx
---x xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
--xx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xx0x 0000
POR, BOR
DS39635A-page 75
Value on
on page:
59, 213
59, 220
59, 218
59, 210
59, 211
59, 114
59, 108
59, 113
59, 107
59, 110
59, 112
59, 106
59, 109
59, 139
59, 137
60, 135
60, 133
60, 131
60, 128
60, 125
60, 122
60, 119
60, 139
60, 137
60, 135
60, 133
60, 131
60, 128
60, 125
60, 122
60, 119
60, 139
60, 137
60, 135
60, 133
60, 131
60, 128
60, 125
60, 122
60, 119
Details
59, 111
59, 89
33, 59