DSPIC33FJ32GP302-I/SO Microchip Technology, DSPIC33FJ32GP302-I/SO Datasheet - Page 114

• Manufacturer Part Number: DSPIC33FJ32GP302-I/SO
• Description: IC DSPIC MCU/DSP 32K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ32GP302-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 21
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 21
• Data Ram Size: 4 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
• Minimum Operating Temperature: - 40 C
• Package: 28SOIC W
• Device Core: dsPIC
• Family Name: dsPIC33
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3 V
• Interface Type: I2C/SPI/UART
• On-chip Adc: 10-chx10-bit|10-chx12-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
10.2
In addition to the PORT, LAT and TRIS registers for
data control, some port pins can also be individually
configured for either digital or open-drain output. This is
controlled by the Open-Drain Control register, ODCx,
associated with each port. Setting any of the bits
configures the corresponding pin to act as an
open-drain output.
The open-drain feature allows the generation of
outputs higher than V
tolerant pins by using external pull-up resistors. The
maximum open-drain voltage allowed is the same as
the maximum V
See “Pin Diagrams” for the available pins and their
functionality.
10.3
The AD1PCFG and TRIS registers control the
operation of the analog-to-digital (A/D) port pins. The
port pins that are desired as analog inputs must have
their corresponding TRIS bit set (input). If the TRIS bit
is cleared (output), the digital output level (V
will be converted.
The AD1PCFGL register has a default value of 0x0000;
therefore, all pins that share ANx functions are analog
(not digital) by default.
When the PORT register is read, all pins configured as
analog input channels will read as cleared (a low level).
Pins configured as digital inputs will not convert an
analog input. Analog levels on any pin that is defined as
a digital input (including the ANx pins) can cause the
input buffer to consume current that exceeds the
device specifications.
EXAMPLE 10-1:
DS70290F-page 114
MOV
MOV
NOP
btss
0xFF00, W0
W0, TRISBB
PORTB, #13
Open-Drain Configuration
Configuring Analog Port Pins
IH
specification.
DD
PORT WRITE/READ EXAMPLE
(e.g., 5V) on any desired 5V
; Configure PORTB<15:8> as inputs
; and PORTB<7:0> as outputs
; Delay 1 cycle
; Next Instruction
OH
or V
Preliminary
OL
)
10.4
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically this instruction
would be a NOP. An example is shown in Example 10-1.
10.5
The input change notification function of the I/O ports
allows
dsPIC33FJ16GP304 devices to generate interrupt
requests to the processor
change-of-state on selected input pins. This feature
can detect input change-of-states even in Sleep mode,
when the clocks are disabled. Depending on the device
pin count, up to 31 external signals (CNx pin) can be
selected (enabled) for generating an interrupt request
on a change-of-state.
Four control registers are associated with the CN
module. The CNEN1 and CNEN2 registers contain the
interrupt enable control bits for each of the CN input
pins. Setting any of these bits enables a CN interrupt
for the corresponding pins.
Each CN pin also has a weak pull-up connected to it.
The pull-ups act as a current source connected to the
pin, and eliminate the need for external resistors when
push button or keypad devices are connected. The
pull-ups are enabled separately using the CNPU1 and
CNPU2 registers, which contain the control bits for
each of the CN pins. Setting any of the control bits
enables the weak pull-ups for the corresponding pins.
Note:
I/O Port Write/Read Timing
Input Change Notification
the
Pull-ups on change notification pins
should always be disabled when the port
pin is configured as a digital output.
dsPIC33FJ32GP202/204
 2009 Microchip Technology Inc.
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