DSPIC33FJ32GP302-I/SO Microchip Technology, DSPIC33FJ32GP302-I/SO Datasheet - Page 58
![IC DSPIC MCU/DSP 32K 28SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
DSPIC33FJ32GP302-I/SO
Manufacturer Part Number
DSPIC33FJ32GP302-I/SO
Description
IC DSPIC MCU/DSP 32K 28SOIC
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ32GP204-IPT.pdf
(14 pages)
2.DSPIC33FJ32GP302-ISO.pdf
(412 pages)
3.DSPIC33FJ64GP804-IML.pdf
(402 pages)
4.DSPIC33FJ32GP204-IPT.pdf
(270 pages)
Specifications of DSPIC33FJ32GP302-I/SO
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
28-SOIC (7.5mm Width)
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
21
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Data Ram Size
4 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Package
28SOIC W
Device Core
dsPIC
Family Name
dsPIC33
Maximum Speed
40 MHz
Operating Supply Voltage
3.3 V
Interface Type
I2C/SPI/UART
On-chip Adc
10-chx10-bit|10-chx12-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- DSPIC33FJ32GP204-IPT PDF datasheet
- DSPIC33FJ32GP302-ISO PDF datasheet #2
- DSPIC33FJ64GP804-IML PDF datasheet #3
- DSPIC33FJ32GP204-IPT PDF datasheet #4
- Current page: 58 of 270
- Download datasheet (2Mb)
dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
5.2
The
dsPIC33FJ16GP304 Flash program memory array is
organized into rows of 64 instructions or 192 bytes.
RTSP allows the user application to erase a page of
memory, which consists of eight rows (512 instructions)
at a time, and to program one row or one word at a
time. The 8-row erase pages and single row write rows
are edge-aligned from the beginning of program
memory, on boundaries of 1536 bytes and 192 bytes,
respectively.
The program memory implements holding buffers that
can contain 64 instructions of programming data. Prior
to the actual programming operation, the write data
must be loaded into the buffers sequentially. The
instruction words loaded must always be from a group
of 64 boundary.
The basic sequence for RTSP programming is to set up
a Table Pointer, then do a series of TBLWT instructions
to load the buffers. Programming is performed by
setting the control bits in the NVMCON register. A total
of 64 TBLWTL and TBLWTH instructions are required
to load the instructions.
All of the table write operations are single-word writes
(two instruction cycles) because only the buffers are
written.
programming each row.
DS70290F-page 58
RTSP Operation
A
programming
dsPIC33FJ32GP202/204
cycle
is
required
and
Preliminary
for
5.3
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode.
programming operation is finished.
The programming time depends on the FRC accuracy
(see Table 22-18, “AC Characteristics: Internal RC
Accuracy”) and the value of the FRC Oscillator Tuning
register (see Register 8-4). Use the following formula to
calculate the minimum and maximum values for the
Row Write Time, Page Erase Time, and Word Write
Cycle Time parameters (see Table 22-12, “DC
Characteristics: Program Memory”).
EQUATION 5-1:
For example, if the device is operating at +125C, the
FRC accuracy will be ±5%. If the TUN<5:0> bits (see
Register 8-4) are set to ‘b111111, the Minimum Row
Write Time is:
and, the Maximum Row Write Time is:
Setting the WR bit (NVMCON<15>) starts the opera-
tion, and the WR bit is automatically cleared when the
operation is finished.
5.4
Two SFRs are used to read and write the program
Flash memory:
• NVMCON: Flash Memory Control Register
• NVMKEY: Nonvolatile Memory Key Register
The NVMCON register (Register 5-1) controls which
blocks are to be erased, which memory type is to be
programmed and the start of the programming cycle.
NVMKEY (Register 5-2) is a write-only register that is
used for write protection. To start a programming or
erase
consecutively write 0x55 and 0xAA to the NVMKEY
register.
Operations” for further details.
T
T
RW
RW
------------------------------------------------------------------------------------------------------------------------- -
7.37 MHz
=
=
---------------------------------------------------------------------------------------------- 1.435ms
7.37 MHz
--------------------------------------------------------------------------------------------- - 1.586ms
7.37 MHz
sequence,
The
Programming Operations
Control Registers
Refer
processor
FRC Accuracy
to
11064 Cycles
11064 Cycles
1
1 0.05
+
the
–
PROGRAMMING TIME
0.05
2009 Microchip Technology Inc.
Section 5.3
T
stalls
user
%
1 0.00375
1 0.00375
–
–
(waits)
application
FRC Tuning
“Programming
=
=
until
%
must
the
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