DSPIC33FJ32GP302-I/SO Microchip Technology, DSPIC33FJ32GP302-I/SO Datasheet - Page 155
![IC DSPIC MCU/DSP 32K 28SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
DSPIC33FJ32GP302-I/SO
Manufacturer Part Number
DSPIC33FJ32GP302-I/SO
Description
IC DSPIC MCU/DSP 32K 28SOIC
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ32GP204-IPT.pdf
(14 pages)
2.DSPIC33FJ32GP302-ISO.pdf
(412 pages)
3.DSPIC33FJ64GP804-IML.pdf
(402 pages)
4.DSPIC33FJ32GP204-IPT.pdf
(270 pages)
Specifications of DSPIC33FJ32GP302-I/SO
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
28-SOIC (7.5mm Width)
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
21
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Data Ram Size
4 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Package
28SOIC W
Device Core
dsPIC
Family Name
dsPIC33
Maximum Speed
40 MHz
Operating Supply Voltage
3.3 V
Interface Type
I2C/SPI/UART
On-chip Adc
10-chx10-bit|10-chx12-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- DSPIC33FJ32GP204-IPT PDF datasheet
- DSPIC33FJ32GP302-ISO PDF datasheet #2
- DSPIC33FJ64GP804-IML PDF datasheet #3
- DSPIC33FJ32GP204-IPT PDF datasheet #4
- Current page: 155 of 270
- Download datasheet (2Mb)
16.0
The Inter-Integrated Circuit (I
complete hardware support for both Slave and
Multi-Master modes of the I
standard, with a 16-bit interface.
The I
• The SCLx pin is clock
• The SDAx pin is data
The I
• I
• I
• I
• I
• Serial clock synchronization for I
• I
2009 Microchip Technology Inc.
modes of operation.
master and slaves.
used as a handshake mechanism to suspend and
resume serial transfer (SCLREL control).
collision and arbitrates accordingly.
Note 1: This data sheet summarizes the features
2
2
2
2
2
C interface supporting both Master and Slave
C Slave mode supports 7-bit and 10-bit address.
C Master mode supports 7-bit and 10-bit address.
C port allows bidirectional transfers between
C supports multi-master operation, detects bus
2
2
C module has a 2-pin interface:
C module offers the following key features:
2: Some registers and associated bits
INTER-INTEGRATED
CIRCUIT™ (I
of
dsPIC33FJ16GP304 family of devices. It
is not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to
Section 19. “Inter-Integrated Circuit™
(I
PIC24H
which is available on the Microchip
website (www.microchip.com).
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
2
C™)” (DS70195) of the “dsPIC33F/
the
dsPIC33FJ32GP202/204 and
Family
2
C™)
2
C serial communication
Reference
2
C) module provides
2
C port can be
Manual”,
Preliminary
16.1
The hardware fully implements all the master and slave
functions of the I
specifications, as well as 7 and 10-bit addressing.
The I
master on an I
The following types of I
• I
• I
• I
For details about the communication sequence in each
of these modes, refer to the “dsPIC33F/PIC24H Family
Reference Manual”.
16.2
I2CxCON and I2CxSTAT are control and status
registers, respectively. The I2CxCON register is
readable and writable. The lower six bits of I2CxSTAT
are read-only. The remaining bits of the I2CSTAT are
read/write.
• I2CxRSR is the shift register used for shifting
• I2CxRCV is the receive buffer and the register to
• I2CxTRN is the transmit register to which bytes
• The I2CxADD register holds the slave address.
• A status bit, ADD10, indicates 10-bit Address
• I2CxBRG acts as the Baud Rate Generator
In receive operations, I2CxRSR and I2CxRCV together
form a double-buffered receiver. When I2CxRSR
receives a complete byte, it is transferred to I2CxRCV,
and an interrupt pulse is generated.
data.
which data bytes are written, or from which data
bytes are read.
are written during a transmit operation.
mode.
(BRG) reload value.
2
2
2
C slave operation with 7-bit address
C slave operation with 10-bit address
C master operation with 7- or 10-bit address
2
C module can operate either as a slave or a
Operating Modes
I
2
C Registers
2
C bus.
2
C Standard and Fast mode
2
C operation are supported:
DS70290F-page 155
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