DSPIC33FJ32GP302-I/SO Microchip Technology, DSPIC33FJ32GP302-I/SO Datasheet - Page 188

• Manufacturer Part Number: DSPIC33FJ32GP302-I/SO
• Description: IC DSPIC MCU/DSP 32K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ32GP302-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 21
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 21
• Data Ram Size: 4 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
• Minimum Operating Temperature: - 40 C
• Package: 28SOIC W
• Device Core: dsPIC
• Family Name: dsPIC33
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3 V
• Interface Type: I2C/SPI/UART
• On-chip Adc: 10-chx10-bit|10-chx12-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
19.5
dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
devices implement a JTAG interface, which supports
boundary scan device testing, as well as in-circuit
programming. Detailed information on this interface will
be provided in future revisions of the document.
19.6
The
dsPIC33FJ16GP304
intermediate implementation of CodeGuard™ Security.
CodeGuard Security enables multiple parties to
securely share resources (memory, interrupts and
TABLE 19-3:
DS70290F-page 188
BSS<2:0> = x11
BSS<2:0> = x10
BSS<2:0> = x01
BSS<2:0> = x00
CONFIG BITS
1792
256
768
0K
JTAG Interface
Code Protection and
CodeGuard™ Security
dsPIC33FJ32GP202/204
CODE FLASH SECURITY
SEGMENT SIZES FOR
32 KBYTE DEVICES
product
GS = 10240 IW
GS = 11008 IW
GS = 7168 IW
GS = 3072 IW
BS = 3840 IW
BS = 7936 IW
VS = 256 IW
VS = 256 IW
BS = 768 IW
VS = 256 IW
VS = 256 IW
families
0001FEh
000200h
0007FEh
000800h
001FFEh
002000h
003FFEh
0057FEh
0007FEh
003FFEh
0057FEh
0001FEh
000200h
0007FEh
000800h
001FFEh
002000h
003FFEh
0057FEh
0001FEh
000200h
0007FEh
000800h
001FFEh
002000h
003FFEh
0057FEh
000000h
004000h
000000h
0001FEh
000200h
000800h
001FFEh
002000h
004000h
000000h
004000h
000000h
004000h
offer
and
Preliminary
the
peripherals) on a single chip. This feature helps protect
individual Intellectual Property in collaborative system
designs.
When coupled with software encryption libraries, Code-
Guard™ Security can be used to securely update Flash
even when multiple IPs reside on the single chip.
The code protection features are controlled by the
Configuration registers: FBS and FGS. The Secure
segment and RAM is not implemented.
TABLE 19-4:
BSS<2:0> = x11
BSS<2:0> = x10
BSS<2:0> = x01
BSS<2:0> = x00
Note:
CONFIG BITS
1792
256
768
0K
Refer
Reference Manual” (DS70180) for further
information on usage, configuration and
operation of CodeGuard Security.
SEGMENT SIZES FOR
16 KBYTE DEVICES
CODE FLASH SECURITY
to
 2009 Microchip Technology Inc.
GS = 5376 IW
GS = 4608 IW
GS = 1536 IW
BS = 3840 IW
BS = 5376 IW
VS = 256 IW
VS = 256 IW
BS = 768 IW
VS = 256 IW
VS = 256 IW
“CodeGuard™
002BFEh
002BFEh
002BFEh
002BFEh
0001FEh
000200h
0007FEh
000800h
001FFEh
002000h
000000h
0001FEh
000200h
0007FEh
000800h
001FFEh
002000h
000000h
0001FEh
000200h
0007FEh
000800h
001FFEh
002000h
000000h
0001FEh
000200h
0007FEh
000800h
001FFEh
002000h
000000h
Security