DSPIC33FJ32GP302-I/SO Microchip Technology, DSPIC33FJ32GP302-I/SO Datasheet - Page 57

• Manufacturer Part Number: DSPIC33FJ32GP302-I/SO
• Description: IC DSPIC MCU/DSP 32K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ32GP302-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 21
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 21
• Data Ram Size: 4 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
• Minimum Operating Temperature: - 40 C
• Package: 28SOIC W
• Device Core: dsPIC
• Family Name: dsPIC33
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3 V
• Interface Type: I2C/SPI/UART
• On-chip Adc: 10-chx10-bit|10-chx12-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.0
The
dsPIC33FJ16GP304 devices contain internal Flash
program memory for storing and executing application
code. The memory is readable, writable and erasable
during normal operation over the entire V
Flash memory can be programmed in two ways:
• In-Circuit Serial Programming™ (ICSP™)
• Run-Time Self-Programming (RTSP)
ICSP
dsPIC33FJ16GP304 device to be serially programmed
while in the end application circuit. This is done with
two lines for programming clock and programming data
(one of the alternate programming pin pairs:
PGECx/PGEDx), and three other lines for power (V
FIGURE 5-1:
 2009 Microchip Technology Inc.
programming capability
Note 1: This data sheet summarizes the features
allows
2: Some registers and associated bits
FLASH PROGRAM MEMORY
of
dsPIC33FJ16GP304 family of devices. It
is not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to
Section
(DS70191) of the “dsPIC33F/PIC24H
Family Reference Manual”, which is avail-
able
(www.microchip.com).
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
dsPIC33FJ32GP202/204
the
Using
Program Counter
Using
Table Instruction
User/Configuration
Space Select
a
from
dsPIC33FJ32GP202/204 and
dsPIC33FJ32GP202/204
ADDRESSING FOR TABLE REGISTERS
5.
the
“Flash
Microchip
1/0
Programming”
0
DD
TBLPAG Reg
range.
8 bits
website
DD
and
and
Preliminary
),
Program Counter
24-bit EA
24 bits
ground (V
customers to manufacture boards with unprogrammed
devices and then program the digital signal controller
just before shipping the product. This also allows the
most recent firmware or a custom firmware to be pro-
grammed.
RTSP is accomplished using TBLRD (table read) and
TBLWT (table write) instructions. With RTSP, the user
application can write program memory data either in
blocks or ‘rows’ of 64 instructions (192 bytes) at a time
or a single program memory word, and erase program
memory in blocks or ‘pages’ of 512 instructions (1536
bytes) at a time.
5.1
Regardless of the method used, all programming of
Flash memory is done with the table read and table
write instructions. These allow direct read and write
access to the program memory space from the data
memory while the device is in normal operating mode.
The 24-bit target address in the program memory is
formed using bits <7:0> of the TBLPAG register and the
Effective Address (EA) from a W register specified in
the table instruction, as shown in Figure 5-1.
The TBLRDL and the TBLWTL instructions are used to
read or write to bits<15:0> of program memory.
TBLRDL and TBLWTL can access program memory in
both Word and Byte modes.
The TBLRDH and TBLWTH instructions are used to read
or write to bits<23:16> of program memory. TBLRDH
and TBLWTH can also access program memory in Word
or Byte mode.
Working Reg EA
16 bits
Table Instructions and Flash
Programming
SS
) and Master Clear (MCLR). This allows
0
Byte
Select
DS70290F-page 57