ATXMEGA64A1-AU Atmel, ATXMEGA64A1-AU Datasheet - Page 63

• Manufacturer Part Number: ATXMEGA64A1-AU
• Description: MCU AVR 64K FLASH 1.6V 100-TQFP
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA64A1-AU

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: ATXMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 4 KB
• Interface Type: I2C/SPI/USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 78
• Number Of Timers: 8
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (8-ch x 12-bit)
• On-chip Dac: 2 (2-ch x 12-bit)
• Package: 100TQFP
• Device Core: AVR
• Family Name: XMEGA
• Maximum Speed: 32 MHz
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFPATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Notes:
8067M–AVR–09/10
Mnemonics
ROL
ROR
ASR
SWAP
BSET
BCLR
SBI
CBI
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
CLI
SES
CLS
SEV
CLV
SET
CLT
SEH
CLH
BREAK
NOP
SLEEP
WDR
1. Cycle times for Data memory accesses assume internal memory accesses, and are not valid for accesses via the external
2. One extra cycle must be added when accessing Internal SRAM.
RAM interface.
Operands
Rd
Rd
Rd
Rd
s
s
A, b
A, b
Rr, b
Rd, b
Description
Rotate Left Through Carry
Rotate Right Through Carry
Arithmetic Shift Right
Swap Nibbles
Flag Set
Flag Clear
Set Bit in I/O Register
Clear Bit in I/O Register
Bit Store from Register to T
Bit load from T to Register
Set Carry
Clear Carry
Set Negative Flag
Clear Negative Flag
Set Zero Flag
Clear Zero Flag
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Two’s Complement Overflow
Clear Two’s Complement Overflow
Set T in SREG
Clear T in SREG
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
Break
No Operation
Sleep
Watchdog Reset
MCU Control Instructions
(See specific descr. for BREAK)
(see specific descr. for Sleep)
(see specific descr. for WDR)
SREG(s)
SREG(s)
I/O(A, b)
I/O(A, b)
Rd(n+1)
Rd(3..0)
Rd(0)
Rd(7)
Rd(n)
Rd(n)
Rd(b)
Operation
C
C
C
C
N
N
H
H
T
Z
Z
S
S
V
V
T
T
I
I
←
←
←
←
←
←
←
↔
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
C,
Rd(n),
Rd(7)
C,
Rd(n+1),
Rd(0)
Rd(n+1), n=0..6
Rd(7..4)
1
0
1
0
Rr(b)
T
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
XMEGA A1
Flags
Z,C,N,V,H
Z,C,N,V
Z,C,N,V
None
SREG(s)
SREG(s)
None
None
T
None
C
C
N
N
Z
Z
I
I
S
S
V
V
T
T
H
H
None
None
None
None
#Clocks
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
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