ATXMEGA64A1-AU Atmel, ATXMEGA64A1-AU Datasheet - Page 97

• Manufacturer Part Number: ATXMEGA64A1-AU
• Description: MCU AVR 64K FLASH 1.6V 100-TQFP
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA64A1-AU

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: ATXMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 4 KB
• Interface Type: I2C/SPI/USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 78
• Number Of Timers: 8
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (8-ch x 12-bit)
• On-chip Dac: 2 (2-ch x 12-bit)
• Package: 100TQFP
• Device Core: AVR
• Family Name: XMEGA
• Maximum Speed: 32 MHz
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFPATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8067M–AVR–09/10
33. RTC Counter value not correctly read after sleep
34. Pending asynchronous RTC-interrupts will not wake up device
35. TWI, the minimum I
36. TWI address-mask feature is non-functional
37. TWI, a general address call will match independent of the R/W-bit value
38. TWI Transmit collision flag not cleared on repeated start
If EBI Power Reduction Bit is set while EBI is enabled, accessing external memory could
result in bus hang-up, blocking all further access to all data memory.
Problem fix/Workaround
Ensure that EBI is disabled before setting EBI Power Reduction bit.
If the RTC is set to wake up the device on RTC Overflow and bit 0 of RTC CNT is identical to
bit 0 of RTC PER as the device is entering sleep, the value in the RTC count register can not
be read correctly within the first prescaled RTC clock cycle after wakeup. The value read will
be the same as the value in the register when entering sleep.
The same applies if RTC Compare Match is used as wake-up source.
Problem fix/Workaround
Wait at least one prescaled RTC clock cycle before reading the RTC CNT value.
Asynchronous Interrupts from the Real-Time-Counter that is pending when the sleep
instruction is executed, will be ignored until the device is woken from another source or the
source triggers again.
Problem fix/Workaround
None.
If the TWI is in Master Read mode and issues a Repeated Start on the bus, this will immedi-
ately release the SCL line even if one complete SCL low period has not passed. This means
that the minimum SCL low time in the I2C specification could be violated.
Problem fix/Workaround
If this is a problem in the application, ensure in software that the Repeated Start is never
issued before one SCL low time has passed.
The address-mask feature is non-functional, so the TWI can not perform hardware address
match on more than one address.
Problem fix/Workaround
If the TWI must respond to multiple addresses, enable Promiscuous Mode for the TWI to
respond to all address and implement the address-mask function in software.
When the TWI is in Slave mode and a general address call is issued on the bus, the TWI
Slave will get an address match regardless of the received R/W bit.
Problem fix/Workaround
Use software to check the R/W-bit on general call address match.
The TWI transmit collision flag should be automatically cleared on start and repeated start,
but is only cleared on start.
2
C SCL low time could be violated in Master Read mode
XMEGA A1
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