AT91M40800-33AU Atmel, AT91M40800-33AU Datasheet - Page 32

• Manufacturer Part Number: AT91M40800-33AU
• Description: IC ARM7 MCU 100 LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91M40800-33AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100TQFP
• Device Core: ARM7TDMI
• Family Name: 91M
• Maximum Speed: 33 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 32
• Interface Type: EBI/USART
• Number Of Timers: 3
• Processor Series: AT91Mx
• Core: ARM7TDMI
• Data Ram Size: 8 KB
• Maximum Clock Frequency: 33 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• Eeprom Memory: 0 Bytes
• Input Output: 32
• Interface: EBI/EMI, UART/USART
• Ios: 32
• Memory Type: ROMless
• Number Of Bits: 32
• Package Type: 100-pin LQFP
• Programmable Memory: 0 Bytes
• Timers: 3-16-bit
• Voltage, Range: 1.8-3.6 V
• Cpu Family: 91M
• Device Core Size: 32b
• Frequency (max): 33MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 8KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.8V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chip Select Change Wait
States
32
AT91X40 Series
Additional constraints are applicable to the AT91R40807, the AT91M40807 and the
AT91 40800. The behavior of the EBI is correct when NWAIT is asserted during an
external memory access:
•
•
These constraints are not applicable to the AT91R40008.
A chip select wait state is automatically inserted when consecutive accesses are made
to two different external memories (if no wait states have already been inserted). If any
wait states have already been inserted, (e.g., data float wait) then none are added.
Figure 21. Chip Select Wait
Notes:
When NWAIT is asserted before the first rising edge of MCKI
When NWAIT is de-asserted and at least one standard wait state remains to be
executed
1. Early Read Protocol
2. Standard Read Protocol
NCS1
NCS2
NWE
NRD
MCK
(1)
Mem 1
(2)
Chip Select Wait
Mem 2
1354D–ATARM–08/02