AT91M40800-33AU Atmel, AT91M40800-33AU Datasheet - Page 90

• Manufacturer Part Number: AT91M40800-33AU
• Description: IC ARM7 MCU 100 LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91M40800-33AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100TQFP
• Device Core: ARM7TDMI
• Family Name: 91M
• Maximum Speed: 33 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 32
• Interface Type: EBI/USART
• Number Of Timers: 3
• Processor Series: AT91Mx
• Core: ARM7TDMI
• Data Ram Size: 8 KB
• Maximum Clock Frequency: 33 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• Eeprom Memory: 0 Bytes
• Input Output: 32
• Interface: EBI/EMI, UART/USART
• Ios: 32
• Memory Type: ROMless
• Number Of Bits: 32
• Package Type: 100-pin LQFP
• Programmable Memory: 0 Bytes
• Timers: 3-16-bit
• Voltage, Range: 1.8-3.6 V
• Cpu Family: 91M
• Device Core Size: 32b
• Frequency (max): 33MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 8KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.8V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

WD User Interface
WD Base Address: 0xFFFF8000 (Code Label WD_BASE)
Table 12. WD Memory Map
WD Overflow Mode Register
Name:
Access:
Reset Value: 0
Offset:
• WDEN: Watch Dog Enable (Code Label WD_WDEN)
0 = Watch Dog is disabled and does not generate any signals.
1 = Watch Dog is enabled and generates enabled signals.
• RSTEN: Reset Enable (Code Label WD_RSTEN)
0 = Generation of an internal reset by the Watch Dog is disabled.
1 = When overflow occurs, the Watch Dog generates an internal reset.
• IRQEN: Interrupt Enable (Code Label WD_IRQEN)
0 = Generation of an interrupt by the Watch Dog is disabled.
1 = When overflow occurs, the Watch Dog generates an interrupt.
• EXTEN: External Signal Enable (Code Label WD_EXTEN)
0 = Generation of a pulse on the pin NWDOVF by the Watch Dog is disabled.
1 = When an overflow occurs, a pulse on the pin NWDOVF is generated.
• OKEY: Overflow Access Key (Code Label WD_OKEY)
Used only when writing WD_OMR. OKEY is read as 0.
0x234 = Write access in WD_OMR is allowed.
Other value = Write access in WD_OMR is prohibited.
90
31
23
15
Offset
–
–
7
0x0C
0x00
0x04
0x08
AT91X40 Series
WD_OMR
Read/Write
0x00
Register
Overflow Mode Register
Clock Mode Register
Control Register
Status Register
30
22
14
–
–
6
OKEY
29
21
13
–
–
5
28
20
12
–
–
4
OKEY
EXTEN
27
19
11
–
–
3
WD_OMR
WD_CMR
WD_CR
WD_SR
Name
IRQEN
26
18
10
–
–
2
Read/Write
Read/Write
Read Only
Write Only
Access
RSTEN
25
17
–
–
9
1
1354D–ATARM–08/02
Reset State
WDEN
0
0
–
0
24
16
–
–
8
0