ATMEGA1280V-8AU Atmel, ATMEGA1280V-8AU Datasheet - Page 198

• Manufacturer Part Number: ATMEGA1280V-8AU
• Description: IC MCU AVR 128K FLASH 100-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA1280V-8AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 86
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: 2-Wire/SPI/USART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 86
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 100TQFP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 8 MHz
• Controller Family/series: AVR MEGA
• No. Of I/o's: 86
• Eeprom Memory Size: 4KB
• Ram Memory Size: 8KB
• Cpu Speed: 8MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK503 - STARTER KIT AVR EXP MODULE 100PATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2549M–AVR–09/10
Note:
Assembly Code Example
C Code Example
SPI_MasterInit:
SPI_MasterTransmit:
Wait_Transmit:
void SPI_MasterInit(void)
{
}
void SPI_MasterTransmit(char cData)
{
}
; Set MOSI and SCK output, all others input
ldi
out
; Enable SPI, Master, set clock rate fck/16
ldi
out
ret
; Start transmission of data (r16)
out
; Wait for transmission complete
sbis SPSR,SPIF
rjmp Wait_Transmit
ret
/* Set MOSI and SCK output, all others input */
DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK);
/* Enable SPI, Master, set clock rate fck/16 */
SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0);
/* Start transmission */
SPDR = cData;
/* Wait for transmission complete */
while(!(SPSR & (1<<SPIF)))
1. See “About Code Examples” on page 11.
;
r17,(1<<DD_MOSI)|(1<<DD_SCK)
DDR_SPI,r17
r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0)
SPCR,r17
SPDR,r16
(1)
(1)
ATmega640/1280/1281/2560/2561
198