AT91SAM9XE512-QU Atmel, AT91SAM9XE512-QU Datasheet - Page 322
![MCU ARM9 512K FLASH 208-PQFP](/photos/6/73/67311/313-208-pqfp_sml.jpg)
AT91SAM9XE512-QU
Manufacturer Part Number
AT91SAM9XE512-QU
Description
MCU ARM9 512K FLASH 208-PQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9XE128-QU.pdf
(860 pages)
Specifications of AT91SAM9XE512-QU
Core Processor
ARM9
Core Size
16/32-Bit
Speed
180MHz
Connectivity
EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
208-MQFP, 208-PQFP
Controller Family/series
AT91SAM9xxxxx
No. Of I/o's
96
Ram Memory Size
32KB
Cpu Speed
180MHz
No. Of Timers
2
Rohs Compliant
Yes
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
2-Wire, EBI, I2S, SPI, USART
Maximum Clock Frequency
180 MHz
Number Of Programmable I/os
96
Number Of Timers
6
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Package
208PQFP
Device Core
ARM926EJ-S
Family Name
91S
Maximum Speed
180 MHz
Operating Supply Voltage
1.8|2.5|3.3 V
For Use With
AT91SAM9XE-EK - KIT EVAL FOR AT91SAM9XEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM9XE512-QU
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Quantity:
40 000
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28.4
28.5
28.6
6254C–ATARM–22-Jan-10
USB Clock Controller
Peripheral Clock Controller
Programmable Clock Output Controller
The USB Source Clock is always generated from the PLL B output. If using the USB, the user
must program the PLL to generate a 48 MHz, a 96 MHz or a 192 MHz signal with an accuracy of
± 0.25% depending on the USBDIV bit in CKGR_PLLBR (see
When the PLL B output is stable, i.e., the LOCKB is set:
Figure 28-3. USB Clock Controller
The Power Management Controller controls the clocks of each embedded peripheral by the way
of the Peripheral Clock Controller. The user can individually enable and disable the Master
Clock on the peripherals by writing into the Peripheral Clock Enable (PMC_PCER) and Periph-
eral Clock Disable (PMC_PCDR) registers. The status of the peripheral clock activity can be
read in the Peripheral Clock Status Register (PMC_PCSR).
When a peripheral clock is disabled, the clock is immediately stopped. The peripheral clocks are
automatically disabled after a reset.
In order to stop a peripheral, it is recommended that the system software wait until the peripheral
has executed its last programmed operation before disabling the clock. This is to avoid data cor-
ruption or erroneous behavior of the system.
The bit number within the Peripheral Clock Control registers (PMC_PCER, PMC_PCDR, and
PMC_PCSR) is the Peripheral Identifier defined at the product level. Generally, the bit number
corresponds to the interrupt source number assigned to the peripheral.
The PMC controls
dently programmed via the PMC_PCKx registers.
PCKx can be independently selected between the Slow clock, the PLL A output, the PLL B out-
put and the main clock by writing the CSS field in PMC_PCKx. Each output signal can also be
divided by a power of 2 between 1 and 64 by writing the PRES (Prescaler) field in PMC_PCKx.
Each output signal can be enabled and disabled by writing 1 in the corresponding bit, PCKx of
PMC_SCER and PMC_SCDR, respectively. Status of the active programmable output clocks
are given in the PCKx bits of PMC_SCSR (System Clock Status Register).
• The USB host clock can be enabled by setting the UHP bit in PMC_SCER. To save power on
this peripheral when it is not used, the user can set the UHP bit in PMC_SCDR. The UHP bit
in PMC_SCSR gives the activity of this clock. The USB host port require both the 12/48 MHz
signal and the Master Clock. The Master Clock may be controlled via the Master Clock
Controller.
Source
Clock
USB
2
signals to be output on external pins PCKx. Each signal can be indepen-
AT91SAM9XE128/256/512 Preliminary
USBDIV
Divider
/1,/2,/4
UDP
UHP
Figure
UDP Clock (UDPCK)
UHP Clock (UHPCK)
28-3).
322
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