AT91SAM9XE512-QU Atmel, AT91SAM9XE512-QU Datasheet - Page 840
![MCU ARM9 512K FLASH 208-PQFP](/photos/6/73/67311/313-208-pqfp_sml.jpg)
AT91SAM9XE512-QU
Manufacturer Part Number
AT91SAM9XE512-QU
Description
MCU ARM9 512K FLASH 208-PQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9XE128-QU.pdf
(860 pages)
Specifications of AT91SAM9XE512-QU
Core Processor
ARM9
Core Size
16/32-Bit
Speed
180MHz
Connectivity
EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
208-MQFP, 208-PQFP
Controller Family/series
AT91SAM9xxxxx
No. Of I/o's
96
Ram Memory Size
32KB
Cpu Speed
180MHz
No. Of Timers
2
Rohs Compliant
Yes
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
2-Wire, EBI, I2S, SPI, USART
Maximum Clock Frequency
180 MHz
Number Of Programmable I/os
96
Number Of Timers
6
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Package
208PQFP
Device Core
ARM926EJ-S
Family Name
91S
Maximum Speed
180 MHz
Operating Supply Voltage
1.8|2.5|3.3 V
For Use With
AT91SAM9XE-EK - KIT EVAL FOR AT91SAM9XEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
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Quantity:
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46.2.6
46.2.6.1
46.2.6.2
46.2.6.3
46.2.7
46.2.7.1
46.2.7.2
840
AT91SAM9XE128/256/512 Preliminary
Serial Peripheral Interface (SPI)
Serial Synchronous Controller (SSC)
SPI: Bad Serial Clock Generation on second chip_select when SCBR = 1, CPOL = 1 and NCPHA = 0
SPI: Software Reset must be Written Twice
SPI: Inaccurate RHR.PCS in Variable Mode
SSC: Transmitter Limitations in Slave Mode
SSC: Delay on TD (transmit data signal)
If the SPI is used in the following configuration:
then an additional pulse will be generated on output SPCK during the second transfer.
Do not use a multiple Chip Select configuration where at least one SCRx register is configured
with SCBR = 1 and the others differ from 1 if CPHA = 0 and CPOL = 1.
If all chip selects are configured with Baudrate = 1, the issue does not appear.
If a software reset (SWRST in the SPI control register) is performed, the SPI may not work prop-
erly (the clock is enabled before the chip select.)
The SPI Control Register field SWRST (Software Reset) needs to be written twice to be correctly
set.
When the SPI is configured in master mode, connected to four slaves and the variable periph-
eral mode is selected, the PCS field in the SPI_RDR does not accurately tell which slave the
received data came from if all Chip Selects are used consecutively.
Use DLYBCT field of the SPI Chip Select Register to include a delay between two consecutive
transfers.
If TK is programmed as output and TF is programmed as input, it is impossible to emit data
when start of edge (rising or falling) of synchro with a Start Delay equal to zero.
None.
When:
• master mode
• CPOL = 1 and NCPHA = 0
• multiple chip selects used with one transfer with Baud rate (SCBR) equal to 1 (i.e., when
• transmit with the slowest chip select and then with the fastest one,
• TCMR.START = Receive Start
• TCMR.STTDLY is more than ZERO
• RCMR.START = Start on falling edge/Start on Rising edge/Start on any edge
• RFMR.FSOS = None (input)
serial clock frequency equals the system clock frequency) and the other transfers set with
SCBR not equal to 1
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
6254C–ATARM–22-Jan-10
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