EZ80F91NAA50EG Zilog, EZ80F91NAA50EG Datasheet - Page 132

• Manufacturer Part Number: EZ80F91NAA50EG
• Description: IC ACCLAIM MCU 256KB 144BGA
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91NAA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LBGA
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG, eZ80F910200KITG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4565

PS027001-0707
TMR3_CTL Write
(Timer Enable)
System Clock
Clock Enable
T3 Count
Interrupt
Request
TMRx_RR_H and TMRx_RR_L. Downcounting continues on the next clock edge and
the timer continues to count until disabled. An example of the timer operating in
CONTINUOUS mode is illustrated in
tion is indicated in
Table 51. Example: PRT CONTINUOUS Mode Parameters
Timer Interrupts
The terminal count flag (TMRx_IIR[EOC]) is set to 1 whenever the timer reaches
its end-of-count value in SINGLE PASS mode, or when the timer reloads the start value in
CONTINUOUS mode. The terminal count flag is only set when the timer reaches
(or reloads) from
with the value
The CPU is programmed to poll the EOC bit for the time-out event. Alternatively, an inter-
rupt service request signal is sent to the CPU by setting the TMRx_IER[EOC] bit to 1.
Parameter
Timer Enable
Reload
Prescaler Divider = 4
CONTINUOUS Mode
End of Count Interrupt Enable
Timer Reload Value
Figure 28. Example: PRT CONTINUOUS Mode Operation
X
0000h
0001h
Table
4
, which selects the maximum time-out period.
. The timer interrupt flag is not set to 1 when the timer is loaded
51on page 124.
3
Control Register(s)
TMR
TMR
TMR
TMR
TMR
{TMR
2
Figure 28
x
x
x
x
x
x
_CTL[TIM_EN]
_CTL[RLD]
_CTL[CLK_DIV]
_CTL[TIM_CONT]
_IER[IRQ_EOC_EN]
_RR_H, TMR
1
on page 124. Timer register informa-
4
x
_RR_L}
Programmable Reload Timers
3
Product Specification
Value
1
1
00b
1
1
0004h
eZ80F91 ASSP
2
1
0000h
0000h
,
124