EZ80F91NAA50EG Zilog, EZ80F91NAA50EG Datasheet - Page 133
EZ80F91NAA50EG
Manufacturer Part Number
EZ80F91NAA50EG
Description
IC ACCLAIM MCU 256KB 144BGA
Manufacturer
Zilog
Series
eZ80® AcclaimPlus!™r
Datasheet
1.EZ80F91AZA50SG.pdf
(387 pages)
Specifications of EZ80F91NAA50EG
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
144-LBGA
Processor Series
EZ80F91x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
8 KB
Interface Type
I2C, IrDA, SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F910300ZCOG, eZ80F910200KITG
Minimum Operating Temperature
- 40 C
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-4565
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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eZ80F91 ASSP
Product Specification
125
And when the end-of-count value (
) is reached, the EOC bit is set to 1 and an inter-
0000h
rupt service request signal is passed to the CPU. The interrupt service request signal is
deactivated by a CPU read of the timer interrupt identification register, TMRx_IIR.
All bits in that register are reset by the Read.
The response of the CPU to this interrupt service request is a function of the CPU’s inter-
®
rupt enable flag, IEF1. For more information about this flag, refer to the eZ80
CPU User
Manual (UM0077) available on www.zilog.com.
Timer Input Source Selection
Timers 0–3 features programmable input source selection. By default, the input is taken
from the eZ80F91’s system clock. The timers also use the Real-Time Clock source (50,
60, or 32768 Hz) as their clock sources. The input source for these timers is set using the
timer control register. (TMRx_CTL[CLK_SEL])
Timer Output
The timer count is directed to the GPIO output pins, if required. To enable the Timer
Output feature, the GPIO port pin must be configured as an output and for alternate func-
tions. The GPIO output pin toggles each time the timer reaches its end-of-count value.
In CONTINUOUS mode operation, enabling the Timer Output feature results in a Timer
Output signal period which is twice the timer time-out period. Examples of Timer Output
operation are illustrated in
Figure 29
and
Table 52
on page 126. The initial value for the
timer output is zero.
Logic to support timer output exists in all timers; but for the eZ80F91 device, only Timer
0 and 2 route the actual timer output to the pins. Because Timer 3 uses the T
pins for
OUT
PWMxN signals, the timer outputs are not available when using complementary PWM
outputs. See
Table 52
on page 126 for details.
PS027001-0707
Programmable Reload Timers
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