EZ80F91NAA50EG Zilog, EZ80F91NAA50EG Datasheet - Page 335

• Manufacturer Part Number: EZ80F91NAA50EG
• Description: IC ACCLAIM MCU 256KB 144BGA
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91NAA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LBGA
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG, eZ80F910200KITG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4565

Table 214. EMAC Buffer Size Register
PS027001-0707
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:6]
BUFSZ
[5:0]
TPCF_LEV
EMAC Interrupt Enable Register
Enabling the Receive Overrun interrupt allows software to detect an overrun condition
as soon as it occurs. If this interrupt is not set, then an overrun cannot be detected until
the software processes the Receive packet with the overrun and checks the Receive sta-
tus in the Rx descriptor table. Because the receiver is disabled by an overrun error until
the Rx_OVR bit is cleared in the EMAC_ISTAT register, this packet is the final packet
in the Receive buffer. To re-enable the receiver before all of the Receive packets are
processed and the Receive buffer is empty, software enables this interrupt to detect the
overrun condition early. As it processes the Receive packets, it re-enables the receiver
when the number of free buffers is greater than the number of minimum buffers. See
Table 215
Value
00
01
10
11
00h–3Fh Transmit Pause Control Frame level. 00h disables the
R/W
Description
Set EMAC Rx/Tx buffer size to 256 bytes.
Set EMAC Rx/Tx buffer size to 128 bytes.
Set EMAC Rx/Tx buffer size to 64 bytes.
Set EMAC Rx/Tx buffer size to 32 bytes.
hardware generated transmit pause control frame.
on page 328.
7
0
R/W
6
0
R/W
5
0
(EMAC_BUFSZ = 004Bh)
R/W
4
0
R/W
3
0
R/W
2
0
R/W
Ethernet Media Access Controller
1
0
Product Specification
R/W
0
0
eZ80F91 ASSP
327