MC908JB16DWE Freescale Semiconductor, MC908JB16DWE Datasheet - Page 305
MC908JB16DWE
Manufacturer Part Number
MC908JB16DWE
Description
IC MCU 16K FLASH 6MHZ USB 28SOIC
Manufacturer
Freescale Semiconductor
Series
HC08r
Specifications of MC908JB16DWE
Core Processor
HC08
Core Size
8-Bit
Speed
6MHz
Connectivity
SCI, USB
Peripherals
LED, LVD, POR, PWM
Number Of I /o
21
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
28-SOIC (7.5mm Width)
Processor Series
HC08JB
Core
HC08
Data Bus Width
8 bit
Data Ram Size
384 B
Interface Type
I2C/SCI/SPI/USB
Maximum Clock Frequency
12 MHz
Number Of Programmable I/os
21
Number Of Timers
4
Operating Supply Voltage
5.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
Minimum Operating Temperature
0 C
Controller Family/series
HC08
No. Of I/o's
21
Ram Memory Size
384Byte
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
MC908JB16DWE
Manufacturer:
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Quantity:
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Part Number:
MC908JB16DWE
Manufacturer:
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Quantity:
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18.4.2 Low V
18.5 LVI Control and Configuration
MC68HC908JB16
Freescale Semiconductor
NOTE:
REG
—
Rev. 1.1
Detector
* LVIDR, LVI5OR3, URSTD, and LVID bits are reset by POR (power-on reset) or LVI reset only.
Address:
Reset:
The low V
LVI reset when the V
LVI circuit can be disabled by the setting the LVIDR bit in CONFIG.
There is no LVI circuit for V
Three bits in the configuration register (CONFIG) control the operation
of the LVI module.
LVIDR — LVI Disable Bit for V
LVI5OR3 — LVI Trip Point Voltage Select Bit for V
LVID — LVI Disable Bit for V
Read:
Write:
LVIDR disables the LVI circuit for V
LVI5OR3 selects the trip point voltage of the LVI circuit for V
Section 20. Electrical Specifications
LVID disables the LVI circuit for V
1 = LVI circuit for V
0 = LVI circuit for V
1 = LVI trips at 3.3V
0 = LVI trips at 2.4V
1 = LVI circuit for V
0 = LVI circuit for V
LVIDR
$001F
Bit 7
0*
Figure 18-2. Configuration Register (CONFIG)
REG
Low-Voltage Inhibit (LVI)
LVI5OR3
= Unimplemented
detector circuit monitors the V
0*
6
REG
URSTD
REG
REG
DD
DD
0*
5
voltage falls below the trip voltage. The V
REGA
disabled
enabled
DD
disabled
enabled
REG
LVID
.
0*
4
DD
REG
.
SSREC
for the trip voltage tolerances.
3
0
.
REG
COPRS
voltage and forces a
2
0
DD
Low-Voltage Inhibit (LVI)
STOP
1
0
Technical Data
DD
COPD
. See
Bit 0
REG
0
305
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