C8051F360-GQ Silicon Laboratories Inc, C8051F360-GQ Datasheet - Page 10

• Manufacturer Part Number: C8051F360-GQ
• Description: IC 8051 MCU 32K FLASH 48TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F36xr

Specifications of C8051F360-GQ

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-TQFP, 48-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 39
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 17x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C/SMBus/SPI/UART
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F360DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 21-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 48TQFP
• Device Core: 8051
• Family Name: C8051F36x
• Maximum Speed: 100 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1483 - ADAPTER PROGRAM TOOLSTICK F360770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1412 - BOARD TARGET/PROTO W/C8051F360336-1411 - DAUGHTER CARD TOOLSTCK C8051F362336-1410 - KIT DEV FOR C8051F360 FAMILY
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1407

C8051F360/1/2/3/4/5/6/7/8/9
18. SMBus
19. UART0
20. Enhanced Serial Peripheral Interface (SPI0)
21. Timers
22. Programmable Counter Array
10
Figure 18.1. SMBus Block Diagram ...................................................................... 202
Figure 18.2. Typical SMBus Configuration ............................................................ 203
Figure 18.3. SMBus Transaction ........................................................................... 204
Figure 18.4. Typical SMBus SCL Generation ........................................................ 207
Figure 18.5. Typical Master Transmitter Sequence ............................................... 213
Figure 18.6. Typical Master Receiver Sequence ................................................... 214
Figure 18.7. Typical Slave Receiver Sequence ..................................................... 215
Figure 18.8. Typical Slave Transmitter Sequence ................................................. 216
Figure 19.1. UART0 Block Diagram ...................................................................... 220
Figure 19.2. UART0 Baud Rate Logic ................................................................... 221
Figure 19.3. UART Interconnect Diagram ............................................................. 222
Figure 19.4. 8-Bit UART Timing Diagram .............................................................. 222
Figure 19.5. 9-Bit UART Timing Diagram .............................................................. 223
Figure 19.6. UART Multi-Processor Mode Interconnect Diagram ......................... 224
Figure 20.1. SPI Block Diagram ............................................................................ 234
Figure 20.2. Multiple-Master Mode Connection Diagram ...................................... 237
Figure 20.3. 3-Wire Single Master and 3-Wire Single Slave Mode
Figure 20.4. 4-Wire Single Master Mode and 4-Wire Slave Mode
Figure 20.5. Master Mode Data/Clock Timing ....................................................... 239
Figure 20.6. Slave Mode Data/Clock Timing (CKPHA = 0) ................................... 240
Figure 20.7. Slave Mode Data/Clock Timing (CKPHA = 1) ................................... 240
Figure 20.8. SPI Master Timing (CKPHA = 0) ....................................................... 244
Figure 20.9. SPI Master Timing (CKPHA = 1) ....................................................... 244
Figure 20.10. SPI Slave Timing (CKPHA = 0) ....................................................... 245
Figure 20.11. SPI Slave Timing (CKPHA = 1) ....................................................... 245
Figure 21.1. T0 Mode 0 Block Diagram ................................................................. 249
Figure 21.2. T0 Mode 2 Block Diagram ................................................................. 250
Figure 21.3. T0 Mode 3 Block Diagram ................................................................. 251
Figure 21.4. Timer 2 16-Bit Mode Block Diagram ................................................. 256
Figure 21.5. Timer 2 8-Bit Mode Block Diagram ................................................... 257
Figure 21.6. Timer 3 16-Bit Mode Block Diagram ................................................. 260
Figure 21.7. Timer 3 8-Bit Mode Block Diagram ................................................... 261
Figure 22.1. PCA Block Diagram ........................................................................... 264
Figure 22.2. PCA Counter/Timer Block Diagram ................................................... 265
Figure 22.3. PCA Interrupt Block Diagram ............................................................ 266
Figure 22.4. PCA Capture Mode Diagram ............................................................. 267
Figure 22.5. PCA Software Timer Mode Diagram ................................................. 268
Figure 22.6. PCA High Speed Output Mode Diagram ........................................... 269
Connection Diagram ......................................................................... 237
Connection Diagram ......................................................................... 237
Rev. 1.0