C8051F360-GQ Silicon Laboratories Inc, C8051F360-GQ Datasheet - Page 208

• Manufacturer Part Number: C8051F360-GQ
• Description: IC 8051 MCU 32K FLASH 48TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F36xr

Specifications of C8051F360-GQ

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-TQFP, 48-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 39
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 17x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C/SMBus/SPI/UART
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F360DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 21-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 48TQFP
• Device Core: 8051
• Family Name: C8051F36x
• Maximum Speed: 100 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1483 - ADAPTER PROGRAM TOOLSTICK F360770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1412 - BOARD TARGET/PROTO W/C8051F360336-1411 - DAUGHTER CARD TOOLSTCK C8051F362336-1410 - KIT DEV FOR C8051F360 FAMILY
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1407

C8051F360/1/2/3/4/5/6/7/8/9
208
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit 3:
Bit 2:
Bits 1–0: SMBCS1–SMBCS0: SMBus Clock Source Selection.
SFR Page:
SFR Address:
ENSMB
R/W
Bit7
ENSMB: SMBus Enable.
This bit enables/disables the SMBus interface. When enabled, the interface constantly mon-
itors the SDA and SCL pins.
0: SMBus interface disabled.
1: SMBus interface enabled.
INH: SMBus Slave Inhibit.
When this bit is set to logic ‘1’, the SMBus does not generate an interrupt when slave events
occur. This effectively removes the SMBus slave from the bus. Master Mode interrupts are
not affected.
0: SMBus Slave Mode enabled.
1: SMBus Slave Mode inhibited.
BUSY: SMBus Busy Indicator.
This bit is set to logic ‘1’ by hardware when a transfer is in progress. It is cleared to logic ‘0’
when a STOP or free-timeout is sensed.
EXTHOLD: SMBus Setup and Hold Time Extension Enable.
This bit controls the SDA setup and hold times according to:
0: SDA Extended Setup and Hold Times disabled.
1: SDA Extended Setup and Hold Times enabled.
SMBTOE: SMBus SCL Timeout Detection Enable.
This bit enables SCL low timeout detection. If set to logic ‘1’, the SMBus forces Timer 3 to
reload while SCL is high and allows Timer 3 to count when SCL goes low. If Timer 3 is con-
figured to Split Mode, only the High Byte of the timer is held in reload while SCL is high.
Timer 3 should be programmed to generate interrupts at 25 ms, and the Timer 3 interrupt
service routine should reset SMBus communication.
SMBFTE: SMBus Free Timeout Detection Enable.
When this bit is set to logic ‘1’, the bus will be considered free if SCL and SDA remain high
for more than 10 SMBus clock source periods.
These two bits select the SMBus clock source, which is used to generate the SMBus bit
rate. The selected device should be configured according to Equation 18.1.
all pages
0xC1
SMBCS1
SFR Definition 18.1. SMB0CF: SMBus Clock/Configuration
INH
R/W
Bit6
0
0
1
1
SMBCS0
BUSY
Bit5
R
0
1
0
1
EXTHOLD SMBTOE SMBFTE SMBCS1
R/W
Bit4
Timer 2 High Byte Overflow
Timer 2 Low Byte Overflow
SMBus Clock Source
Timer 0 Overflow
Timer 1 Overflow
Rev. 1.0
R/W
Bit3
R/W
Bit2
R/W
Bit1
SMBCS0 00000000
R/W
Bit0
Reset Value