C8051F360-GQ Silicon Laboratories Inc, C8051F360-GQ Datasheet - Page 151
![IC 8051 MCU 32K FLASH 48TQFP](/photos/12/18/121855/c8051f360-gq_sml.jpg)
C8051F360-GQ
Manufacturer Part Number
C8051F360-GQ
Description
IC 8051 MCU 32K FLASH 48TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F36xr
Specifications of C8051F360-GQ
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
48-TQFP, 48-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
100MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
39
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 17x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
100 MHz
Number Of Programmable I/os
39
Number Of Timers
4
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F360DK
Minimum Operating Temperature
- 40 C
On-chip Adc
21-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
48TQFP
Device Core
8051
Family Name
C8051F36x
Maximum Speed
100 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1483 - ADAPTER PROGRAM TOOLSTICK F360770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1412 - BOARD TARGET/PROTO W/C8051F360336-1411 - DAUGHTER CARD TOOLSTCK C8051F362336-1410 - KIT DEV FOR C8051F360 FAMILY
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1407
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F360-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Part Number:
C8051F360-GQ
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
Company:
Part Number:
C8051F360-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Part Number:
C8051F360-GQR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
- Current page: 151 of 288
- Download datasheet (3Mb)
Bit 7:
Bit 6:
Bit 5:
Bits 4–0: CHSLOT: Cache Slot Pointer.
SFR Page:
SFR Address:
CHPUSH
R/W
Bit7
CHPUSH: Cache Push Enable.
This bit enables cache push operations, which will lock information in cache slots using
MOVC instructions.
0: Cache push operations are disabled.
1: Cache push operations are enabled. When a MOVC read is executed, the requested 4-
Note:No more than 30 cache slots should be locked at one time, since the entire cache will be unlocked
when CHSLOT is equal to 0.
CHPOP: Cache Pop.
Writing a ‘1’ to this bit will increment CHSLOT and then unlock that location. This bit always
reads ‘0’. Note that Cache Pop operations should not be performed while CHSLOT =
11110b. “Pop”ing more Cache slots than have been “Push”ed will have indeterminate results
on the Cache performance.
RESERVED. Read = 0b. Must Write 0b.
These read-only bits are the pointer into the cache lock stack. Locations above CHSLOT are
locked, and will not be changed by the processor, except when CHSLOT equals 0.
F
0xD2
byte segment containing the data is locked into the cache at the location indicated by
CHSLOT, and CHSLOT is decremented.
CHPOP RESERVED
R/W
Bit6
SFR Definition 14.3. CCH0LC: Cache Lock Control
Bit5
R
Bit4
R
C8051F360/1/2/3/4/5/6/7/8/9
Rev. 1.0
Bit3
R
CHSLOT
Bit2
R
Bit1
R
Bit0
R
Reset Value
00011111
151
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