C8051F360-GQ Silicon Laboratories Inc, C8051F360-GQ Datasheet - Page 129

• Manufacturer Part Number: C8051F360-GQ
• Description: IC 8051 MCU 32K FLASH 48TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F36xr

Specifications of C8051F360-GQ

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-TQFP, 48-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 39
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 17x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C/SMBus/SPI/UART
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F360DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 21-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 48TQFP
• Device Core: 8051
• Family Name: C8051F36x
• Maximum Speed: 100 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1483 - ADAPTER PROGRAM TOOLSTICK F360770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1412 - BOARD TARGET/PROTO W/C8051F360336-1411 - DAUGHTER CARD TOOLSTCK C8051F362336-1410 - KIT DEV FOR C8051F360 FAMILY
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1407

12.1. Power-On Reset
During power-up, the device is held in a reset state and the RST pin is driven low until V
V
increases (V
power-on and V
lay
Note: The maximum V
reset before V
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic ‘1’. When PORSF
is set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000) software can
read the PORSF flag to determine if a power-up was the cause of reset. The content of internal data mem-
ory should be assumed to be undefined after a power-on reset. The V
power-on reset.
RST
) is typically less than 0.3 ms.
. A delay occurs before the device is released from reset; the delay decreases as the V
DD
DD
DD
ramp time is defined as how fast V
Logic HIGH
Logic LOW
reaches the V
Figure 12.2. Power-On and V
Monitor reset timing. For ramp times less than 1 ms, the power-on reset delay (T
2.70
2.55
2.0
1.0
DD
ramp time is 1 ms; slower ramp times may cause the device to be released from
/RST
RST
V
RST
level.
Power-On
Reset
T
PORDelay
C8051F360/1/2/3/4/5/6/7/8/9
Rev. 1.0
DD
DD
ramps from 0 V to V
Monitor Reset Timing
Monitor
Reset
VDD
DD
Monitor is enabled following a
RST
). Figure 12.2. plots the
VDD
DD
t
settles above
DD
ramp time
PORDe-
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