MC908GP32CFBE Freescale Semiconductor, MC908GP32CFBE Datasheet - Page 153

• Manufacturer Part Number: MC908GP32CFBE
• Description: IC MCU 8MHZ 32K FLASH 44-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GP32CFBE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 33
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFP
• Processor Series: HC08GP
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

BKF — Break Flag Bit
RPF — Reception in Progress Flag Bit
13.8.6 SCI Data Register
The SCI data register (SCDR) is the buffer between the internal data bus and the receive and transmit
shift registers. Reset has no effect on data in the SCI data register.
R7/T7–R0/T0 — Receive/Transmit Data Bits
13.8.7 SCI Baud Rate Register
The baud rate register (SCBR) selects the baud rate for both the receiver and the transmitter.
Freescale Semiconductor
This clearable, read-only bit is set when the SCI detects a break character on the PTE1/RxD pin. In
SCS1, the FE and SCRF bits are also set. In 9-bit character transmissions, the R8 bit in SCC3 is
cleared. BKF does not generate a CPU interrupt request. Clear BKF by reading SCS2 with BKF set
and then reading the SCDR. Once cleared, BKF can become set again only after logic 1s again appear
on the PTE1/RxD pin followed by another break character. Reset clears the BKF bit.
This read-only bit is set when the receiver detects a logic 0 during the RT1 time period of the start bit
search. RPF does not generate an interrupt request. RPF is reset after the receiver detects false start
bits (usually from noise or a baud rate mismatch) or when the receiver detects an idle character. Polling
RPF before disabling the SCI module or entering stop mode can show whether a reception is in
progress.
Reading the SCDR accesses the read-only received data bits, R7:R0. Writing to the SCDR writes the
data to be transmitted, T7:T0. Reset has no effect on the SCDR.
1 = Break character detected
0 = No break character detected
1 = Reception in progress
0 = No reception in progress
Address:
Address:
Do not use read/modify/write instructions on the SCI data register.
Reset:
Reset:
Read:
Read:
Write:
Write:
$0017
$0018
Bit 7
Bit 7
R7
T7
0
Figure 13-14. SCI Status Register 2 (SCS2)
= Unimplemented
Figure 13-15. SCI Data Register (SCDR)
R6
T6
6
0
6
MC68HC908GP32 Data Sheet, Rev. 10
R5
T5
5
0
5
NOTE
Unaffected by reset
R4
T4
4
0
4
R3
T3
3
0
3
R2
T2
2
0
2
BKF
R1
T1
1
0
1
Bit 0
RPF
Bit 0
R0
T0
0
I/O Registers
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