MC908GP32CFBE Freescale Semiconductor, MC908GP32CFBE Datasheet - Page 190

• Manufacturer Part Number: MC908GP32CFBE
• Description: IC MCU 8MHZ 32K FLASH 44-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GP32CFBE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 33
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFP
• Processor Series: HC08GP
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Serial Peripheral Interface Module (SPI)
15.13 I/O Registers
Three registers control and monitor SPI operation:
15.13.1 SPI Control Register
The SPI control register:
SPRIE — SPI Receiver Interrupt Enable Bit
SPMSTR — SPI Master Bit
CPOL — Clock Polarity Bit
CPHA — Clock Phase Bit
SPWOM — SPI Wired-OR Mode Bit
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This read/write bit enables CPU interrupt requests generated by the SPRF bit. The SPRF bit is set
when a byte transfers from the shift register to the receive data register. Reset clears the SPRIE bit.
This read/write bit selects master mode operation or slave mode operation. Reset sets the SPMSTR
bit.
This read/write bit determines the logic state of the SPSCK pin between transmissions. (See
15-4
CPOL values. Reset clears the CPOL bit.
This read/write bit controls the timing relationship between the serial clock and SPI data. (See
15-4
CPHA values. When CPHA = 0, the SS pin of the slave SPI module must be set to logic 1 between
bytes. (See
This read/write bit disables the pullup devices on pins SPSCK, MOSI, and MISO so that those pins
become open-drain outputs.
1 = SPRF CPU interrupt requests enabled
0 = SPRF CPU interrupt requests disabled
1 = Master mode
0 = Slave mode
SPI control register (SPCR)
SPI status and control register (SPSCR)
SPI data register (SPDR)
Enables SPI module interrupt requests
Configures the SPI module as master or slave
Selects serial clock polarity and phase
Configures the SPSCK, MOSI, and MISO pins as open-drain outputs
Enables the SPI module
and
and
Figure
Figure
Address: $0010
Figure
Reset:
Read:
Write:
15-6.) To transmit data between SPI modules, the SPI modules must have identical
15-6.) To transmit data between SPI modules, the SPI modules must have identical
15-12.) Reset sets the CPHA bit.
SPRIE
Bit 7
0
Figure 15-13. SPI Control Register (SPCR)
R
6
0
MC68HC908GP32 Data Sheet, Rev. 10
SPMSTR
5
1
CPOL
R
4
0
= Reserved
CPHA
3
1
SPWOM
2
0
SPE
1
0
Freescale Semiconductor
SPTIE
Bit 0
0
Figure
Figure