MC9S12C128CFUE Freescale Semiconductor, MC9S12C128CFUE Datasheet - Page 156

• Manufacturer Part Number: MC9S12C128CFUE
• Description: IC MCU 128K FLASH 25MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12C128CFUE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: CAN/SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 60
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/2.97V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Processor Series: S12C
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 4000 B
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 61
• Number Of Timers: 1
• Operating Supply Voltage: - 0.3 V to + 6.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912C32EE
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Chapter 4 Multiplexed External Bus Interface (MEBIV3)
mode. Background debugging should not be used while the MCU is in special peripheral mode as internal
bus conflicts between BDM and the external master can cause improper operation of both functions.
4.4.4
Internal visibility is available when the MCU is operating in expanded wide modes or emulation narrow
mode. It is not available in single-chip, peripheral or normal expanded narrow modes. Internal visibility is
enabled by setting the IVIS bit in the MODE register.
If an internal access is made while E, R/W, and LSTRB are configured as bus control outputs and internal
visibility is off (IVIS=0), E will remain low for the cycle, R/W will remain high, and address, data and the
LSTRB pins will remain at their previous state.
When internal visibility is enabled (IVIS=1), certain internal cycles will be blocked from going external.
During cycles when the BDM is selected, R/W will remain high, data will maintain its previous state, and
address and LSTRB pins will be updated with the internal value. During CPU no access cycles when the
BDM is not driving, R/W will remain high, and address, data and the LSTRB pins will remain at their
previous state.
4.4.5
The MEBI does not contain any user-controlled options for reducing power consumption. The operation
of the MEBI in low-power modes is discussed in the following subsections.
4.4.5.1
The MEBI does not contain any options for reducing power in run mode; however, the external addresses
are conditioned to reduce power in single-chip modes. Expanded bus modes will increase power
consumption.
4.4.5.2
The MEBI does not contain any options for reducing power in wait mode.
4.4.5.3
The MEBI will cease to function after execution of a CPU STOP instruction.
156
Internal Visibility
Low-Power Options
Operation in Run Mode
Operation in Wait Mode
Operation in Stop Mode
When the system is operating in a secure mode, internal visibility is not
available (i.e., IVIS = 1 has no effect). Also, the IPIPE signals will not be
visible, regardless of operating mode. IPIPE1–IPIPE0 will display 0es if
they are enabled. In addition, the MOD bits in the MODE control register
cannot be written.
MC9S12C-Family / MC9S12GC-Family
Rev 01.24
NOTE
Freescale Semiconductor