MC9S12C128CFUE Freescale Semiconductor, MC9S12C128CFUE Datasheet - Page 204

• Manufacturer Part Number: MC9S12C128CFUE
• Description: IC MCU 128K FLASH 25MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12C128CFUE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: CAN/SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 60
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/2.97V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Processor Series: S12C
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 4000 B
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 61
• Number Of Timers: 1
• Operating Supply Voltage: - 0.3 V to + 6.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912C32EE
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Chapter 7 Debug Module (DBGV1) Block Description
7.3.2.6
204
Module Base + 0x0026
Starting address location affected by INITRG register setting.
Module Base + 0x0027
Starting address location affected by INITRG register setting.
PORTK/XAB
PPAGE
Reset
Reset
7
SEE NOTE 1
PAGSEL
W
W
R
R
NOTES:
1. In BKP and DBG mode, PAGSEL selects the type of paging as shown in
2. Current HCS12 implementations are limited to six PPAGE bits, PIX[5:0]. Therefore, EXTCMP[5:4] = 00.
Bit 15
Bit 7
6
Debug Comparator C Register (DBGCC)
15
0
0
7
Figure 7-10. Comparator C Extended Comparison in BKP/DBG Mode
XAB21
PIX7
= Unimplemented or Reserved
= Unimplemented or Reserved
SEE NOTE 2
0
5
Figure 7-11. Debug Comparator C Register High (DBGCCH)
Figure 7-12. Debug Comparator C Register Low (DBGCCL)
Bit 14
Bit 6
14
0
0
6
XAB20
PIX6
0
4
XAB19
PIX5
Bit 13
MC9S12C-Family / MC9S12GC-Family
Bit 5
3
13
0
0
5
DBGCXX
EXTCMP
XAB18
PIX4
2
Rev 01.24
Bit 12
Bit 4
12
0
0
4
XAB17
PIX3
1
XAB16
BIT 0
PIX2
Bit 11
Bit 3
11
0
0
3
Table
XAB15
BIT 15
PIX1
7-11.
Bit 10
Bit 2
10
0
0
2
XAB14
BIT 14
PIX0
DBGCXH[15:12]
BIT 13
Freescale Semiconductor
Bit 9
Bit 1
0
0
9
1
BIT 12
Bit 8
Bit 0
0
0
8
0